US 10,854,471 B2 · Process for making multi-gate transistors and resulting structures

Abstract

In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.

Claims20

Dependent claims

A method, comprising:

forming a first dummy gate structure and a second dummy gate structure on a substrate;
depositing an interlayer dielectric layer surrounding the first dummy gate structure and the second dummy gate structure;
planarizing the interlayer dielectric layer, thereby exposing upper surfaces of the first dummy gate structure and the second dummy gate structure;
removing the first dummy gate structure to form a first recess;
performing a process on the interlayer dielectric layer to improve etch resistivity of the interlayer dielectric layer relative to a predetermined etch process;
after the performing the process, depositing a sacrificial material in the first recess;
removing the second dummy gate structure to form a second recess;
forming a conductive structure in the second recess;
and
planarizing the conductive structure and an upper surface of the interlayer dielectric layer.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/518,505Filed 22 Jul 2019 · continuation

Priority

30 Nov 2016

Published

US 2019/0348298 A114 Nov 2019

Granted

1 Dec 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10P 30/40
Ion implantation into wafers, substrates or parts of devices: into insulating materials
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/6212
Fin field-effect transistors [FinFET]: having fin-shaped semiconductor bodies having non-rectangular cross-sections
H10D 30/6217
Fin field-effect transistors [FinFET]: having non-uniform gate electrodes, e.g. gate conductors having varying doping

Family

Application62/428,447Us provisional application · filed 30 Nov 2016

Application15/441,063Parent of this division · filed 23 Feb 2017

Application16/050,148Parent of this continuation · filed 31 Jul 2018

US 10,177,006 B2Parent of this division · filed 8 Jan 2019

US 2019/0348298 A1Pre-grant publication · published 14 Nov 2019

US 10,361,094 B2Parent of this continuation

Application16/050,148Parent of this division

US 2018/0151387 A1Published application

US 2018/0366341 A1Published application

US 10,854,471 B2This patent

From the US filing history. Foreign family members aren’t listed.

Process for making multi-gate transistors and resulting structures

Life of this patent

Process for making multi-gate transistors and resulting structures

Life of this patent

Abstract

Claims20