Shared error detection and correction memory

An apparatus comprising an interface chip, the interface chip including:

• a direct access test port circuit including a set of test ports;
• a control circuit configured to control the direct access test port circuit to provide a set of groups of test signals from the set of test ports;
• a plurality of circuit blocks including at least one set of circuit blocks, each circuit block among a first set of circuit blocks of the at least one set of circuit blocks configured to receive a first group of test signals of the set of groups of test signals and provide internal signals based on the first group of test signals;
• a plurality of TSV terminals coupled to a plurality of conductive vias, the plurality of TSV terminals including at least one set of TSV terminals;
• and
• a remapping circuit including at least one set of multiplexers with a dummy multiplexer, one multiplexer of the at least one set of multiplexers configured to couple one or more TSV terminals among one set of the at least one set of TSV terminals to a corresponding circuit block of a corresponding set of the at least one set of circuit blocks, wherein the at least one set of multiplexers comprises:
• a set of first multiplexers, each first multiplexer being configured to couple to one or more first TSV terminals among the plurality of TSV terminals to a corresponding first circuit block of the first set of circuit blocks;
• and
• a set of second multiplexers, each second multiplexer being configured to couple to one or more second TSV terminals among the plurality of TSV terminals to a corresponding second circuit block of a second set of circuit blocks.

A method of providing test signals on an interface chip, the method comprising:

• receiving first and second groups of test signals among a set of groups of test signals. wherein the first group of test signals corresponds to a first byte and the second group of test signals corresponds to a second byte:
• receiving an input signal from an interconnect at one circuit block among a plurality of circuit blocks;
• providing internal signals from the one circuit block, based on the first group of first test signals, the second group of test signals, or the input signal;
• selectively coupling the one circuit block to a TSV terminal among a plurality of TSV terminals by a remapping circuit responsive to a corresponding lane shift enable signal;
• and
• providing internal signals based on either the first group of test signals or the second group of test signals to a multiplexer including a first input coupled to the one circuit block and including a second input coupled to another circuit block among the plurality of circuit blocks responsive to the lane shift enable signal.