Apparatus and methods for seeding operations concurrently with data line set operations

A memory, comprising:

• an array of memory cells comprising a first string of series-connected memory cells and a second string of series-connected memory cells;
• and
• a controller for access of the array of memory cells, wherein the controller is configured to:
• perform a sense operation on a particular memory cell of the first string of series-connected memory cells, wherein each memory cell of the first string of series-connected memory cells is connected to a respective access line of a plurality of access lines and is between a first end of the first string of series-connected memory cells and a second end of the first string of series-connected memory cells, and wherein the first end of the first string of series-connected memory cells is selectively connected to a first data line;
• discharge the respective access lines of the plurality of access lines for a first subset of memory cells of the first string of series-connected memory cells to a first voltage level, wherein each memory cell of the first subset of memory cells is between the particular memory cell and the first end of the first string of series-connected memory cells;
• discharge the respective access lines of the plurality of access lines for a second subset of memory cells of the first string of series-connected memory cells to the first voltage level, wherein each memory cell of the second subset of memory cells is between the particular memory cell and the first subset of memory cells;
• discharge the respective access line of the plurality of access lines for the particular memory cell to a second voltage level higher than the first voltage level;
• discharge the respective access lines of the plurality of access lines for a third subset of memory cells of the first string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level, wherein each memory cell of the third subset of memory cells is between the particular memory cell and the second end of the first string of series-connected memory cells;
• discharge the respective access lines of the plurality of access lines for a fourth subset of memory cells of the first string of series-connected memory cells to the first voltage level, wherein each memory cell of the fourth subset of memory cells is between the third subset of memory cells and the second end of the first string of series-connected memory cells;
• apply a fourth voltage level to the first data line concurrently with discharging the respective access lines of the plurality of access lines for the first, second, third, and fourth subsets of memory cells and the particular memory cell;
• and
• apply a fifth voltage level higher than the fourth voltage level to a second data line selectively connected to the second string of series-connected memory cells concurrently with applying the fourth voltage level to the first data line, wherein each memory cell of the second string of series-connected memory cells is connected to a respective access line of the plurality of access lines.

A memory, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• and
• a controller for access of the array of memory cells, wherein the controller is configured to:
• perform a sense operation on a particular memory cell of a first string of series-connected memory cells of the plurality of strings of series-connected memory cells, wherein each memory cell of the first string of series-connected memory cells is connected to a respective access line of a plurality of access lines and is between a first end of the first string of series-connected memory cells and a second end of the first string of series-connected memory cells, and wherein the first end of the first string of series-connected memory cells is selectively connected to a first data line and the second end of the first string of series-connected memory cells is selectively connected to a common source;
• apply a first voltage level to the respective access lines of the plurality of access lines for a first subset of memory cells of the first string of series-connected memory cells;
• apply a second voltage level higher than the first voltage level to the respective access line of the plurality of access lines for the particular memory cell;
• apply a third voltage level to the first data line concurrently with the application of the first voltage level to the respective access lines of the plurality of access lines for the first subset of memory cells of the first string of series-connected memory cells and concurrently with the application of the second voltage level to the respective access line of the plurality of access lines for the particular memory cell;
• and
• apply a fourth voltage level higher than the third voltage level to a second data line selectively connected to a second string of series-connected memory cells of the plurality of strings of series-connected memory cells concurrently with the application of the third voltage level to the first data line, wherein each memory cell of the second string of series-connected memory cells is connected to a respective access line of the plurality of access lines.