US 10,854,299 B2Granted

Data erase operations for a memory system

AssigneeMicron Technology, Inc.

InventorsKevin R. Brandt, Adam J. Hieb, Jonathan Tanguy, Preston A. Thomson

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Abstract

A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.

Claims14

Dependent claims

A method, comprising:

receiving a data erasure command from a host;
responsive to receiving the data erasure command:
identifying a plurality of physical blocks of a memory device that are invalid, wherein:
the plurality of invalid physical blocks were previously invalidated responsive to a bit error rate (BER) associated with a corresponding one of the plurality of invalid blocks exceeding a threshold BER;
and
the plurality of invalid physical blocks store respective data corresponding to information associated with threshold voltage distributions of the plurality of invalid physical blocks;
transferring the data from the plurality of invalid physical blocks to the host from which the data erasure command was issued;
and
performing, subsequent to the data being transferred out of the memory device, a data erase operation on the memory device, wherein the data erase operation results in physical erasure of at least one of the plurality of invalid physical blocks including physical erasure of the data that were previously transferred out of the memory device.

6 more elements

An apparatus, comprising:

a memory device;
and
a controller coupled to the memory device and configured to:
identify, responsive to a receipt of a data erasure command from a host, a plurality of invalid blocks, wherein the plurality of invalid blocks were previously invalidated responsive to a bit error rate (BER) associated with a corresponding one of the plurality of invalid blocks exceeding a threshold BER;
perform a data erase operation on the memory device, wherein:
the data erase operation results in physical erasure of at least one of the plurality of invalid physical blocks;
and
the physical erasure is performed in response to the data erasure command and regardless of a number of erase operations previously performed on the at least one of the plurality of invalid physical blocks;
and
prior to performing the data erase operation:
transfer, from the at least one of the plurality of invalid physical blocks to the host where the data erasure command was issued from, data corresponding to information associated with corresponding failing scenes of the at least one of the plurality of invalid physical blocks, wherein the data erase operation performed on the at least one of the plurality of invalid physical blocks results in physical erasure of the data corresponding to the information associated with corresponding failing scenes of the at least one of the plurality of invalid physical blocks.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/994,151Filed 31 May 2018
Published: US 2019/0371409 A15 Dec 2019
Granted: 1 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G11C 16/16
Circuits for erasing electrically, e.g. erase voltage switching circuits: for erasing blocks, e.g. arrays, words, groups
G11C 7/20
Arrangements for writing information into, or reading information out from, a digital store: memory cell initialisation circuits, e.g. when…
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C
Static stores