I/O buffer offset mitigation

A method of operating an integrated circuit device, comprising:

• applying a particular voltage level to a first input of an input buffer of the integrated circuit device through an on-die termination device;
• applying the particular voltage level to a second input of the input buffer;
• determining whether the input buffer is deemed to exhibit offset;
• applying an adjustment to the input buffer offset while applying the particular voltage level to the first input of the input buffer and to the second input of the input buffer if the input buffer is deemed to exhibit offset;
• increasing a magnitude of the adjustment until a logic level of an output of the input buffer transitions;
• and
• in response to the transition, storing trim settings for the integrated circuit device corresponding to the adjustment resulting in the transition.

A memory, comprising:

• an array of memory cells;
• an input buffer having a first input, a second input, and an output configured for providing signals for use in storing data to the array of memory cells;
• and
• calibration logic selectively connected to the output of the input buffer and configured to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first input of the input buffer and to the second input of the input buffer, and to apply an adjustment to the offset of the input buffer while applying the particular voltage level to the first input of the input buffer and to the second input of the input buffer until a logic level of the output of the input buffer transitions.