Semiconductor memory device having pass transistors
AssigneeSK hynix Inc.
InventorsJin Ho Kim, Jeong Hwan Kim, Sang Hyun Sung, Sung Lae Oh
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a plurality of memory cell arrays accessed through a plurality of row lines and a plurality of bit lines; a pass transistor coupled to one of the plurality of row lines and configured to transfer an operating voltage to the one of the plurality of row lines; and a plurality of wiring lines disposed in a wiring line layer over the pass transistor. The wiring line layer includes a wiring inhibition interval which overlaps a source and a drain of the pass transistor. One or more of the plurality of wiring lines is disposed outside of the wiring inhibition interval.
Claims21
A semiconductor memory device comprising:
- a plurality of memory cell arrays accessed through a plurality of row lines and a plurality of bit lines;
- a pass transistor coupled to one of the plurality of row lines and configured to transfer an operating voltage to the one of the plurality of row lines;
- and
- a plurality of wiring lines disposed in a wiring line layer over the pass transistor,
- wherein the wiring line layer comprises a wiring inhibition interval which overlaps a source and a drain of the pass transistor,
- wherein one or more of the plurality of wiring lines is disposed outside of the wiring inhibition interval.
A semiconductor memory device comprising:
- a memory structure disposed on a first substrate, and comprising a plurality of memory cell arrays which are accessed through a plurality of row lines and a plurality of bit lines;
- and
- a logic structure disposed on a second substrate, and comprising a logic circuit which comprises a pass transistor coupled to one of the plurality of row lines and transferring an operating voltage to the one of the plurality of row lines and a plurality of wiring lines disposed in a wiring line layer over the logic circuit,
- wherein the wiring line layer comprises a wiring inhibition interval which overlaps with a source and a drain of the pass transistor and excludes at least one of the wiring lines.
Dependencies are inferred from the claim text.