Resistive memory device providing reference calibration, and operating method thereof

A resistive memory device configured to calibrate a plurality of reference resistors, the resistive memory device comprising:

• a calibration resistor;
• a plurality of reference resistors;
• a plurality of sense amplifiers each configured to compare a reference current passing through one of the plurality of reference resistors with a read current passing through a memory cell during a read operation, and compare the reference current with a calibration current passing through the calibration resistor during a calibration operation;
• a plurality of second switches configured to form a second path during a calibrate operation to allow the reference current to pass through the second path;
• and
• a plurality of first switches configured to form a first path across a row in which the sense amplifiers are arranged from one of the sense amplifiers to the calibration resistor through which the calibration current passes during the calibration operation,
• wherein the second path has substantially the same length as the first path.

A resistive memory device configured to calibrate a plurality of reference resistors, the resistive memory device comprising:

• a calibration resistor;
• a plurality of read circuits each configured to compare a reference current passing through one of a plurality of reference resistors with a read current passing through a memory cell during a read operation, and compare the reference current with a calibration current passing through the calibration resistor during a calibrate operation;
• a first conductive line connected to the plurality of read circuits and the calibration resistor, and configured to allow the calibration current to pass therethrough during the calibrate operation;
• and
• a second conductive line connected to the plurality of read circuits, and configured to allow the reference current to pass therethrough during the calibrate operation,
• wherein the first conductive line crosses a row in which the read circuits are arranged,
• wherein the first conductive line and the second conductive line have substantially the same length as each other.