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US 10,854,288 B2Granted
Semiconductor memory apparatus for preventing disturbance
AssigneeSK hynix Inc.
InventorJin Su Park
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes an access line control circuit. The access line control circuit applies a selected bias voltage to a selected access line coupled with a target memory cell and applies a first unselected bias voltage to an unselected access line adjacent to the selected access line. A second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line.
Claims12
A semiconductor memory apparatus comprising:
- an access line control circuit configured to apply a selected bias voltage to a selected access line coupled with a target memory cell and configured to apply a first unselected bias voltage to an unselected access line adjacent to the selected access line,
- wherein a second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line.
A semiconductor memory apparatus comprising:
- a bit line control circuit configured to apply a selected bit line bias voltage to a selected bit line coupled with a target memory cell and configured to apply a first unselected bit line bias voltage to an unselected bit line adjacent to the selected bit line;
- and
- a word line control circuit configured to apply a selected word line bias voltage to a selected word line coupled with the target memory cell and configured to apply a first unselected word line bias voltage to an unselected word line adjacent to the selected word line,
- wherein a second unselected bit line bias voltage is applied to an unselected bit line not adjacent to the selected bit line, and
- wherein a second unselected word line bias voltage is applied to an unselected word line not adjacent to the selected word line.
2 more elements
A semiconductor memory apparatus comprising:
- a bit line control circuit configured to apply a selected bit line bias voltage to a selected bit line coupled with a target memory cell and configured to apply a bit line voltage, having a voltage level between a first unselected bit line bias voltage and a second unselected bit line bias voltage, which is higher in proportion to a distance from the selected bit line to an unselected bit line to which the bit line voltage is applied;
- and
- a word line control circuit configured to apply a selected word line bias voltage to a selected word line coupled with the target memory cell and configured to apply a word line voltage, having a voltage level between a first unselected word line bias voltage and a second unselected word line bias voltage, which is lower in proportion to a distance from the selected word line to an unselected word line to which the word line voltage is applied.
Dependencies are inferred from the claim text.