Back to results
US 10,854,284 B1Granted
Computational memory cell and processing array device with ratioless write port
AssigneeGSI Technology, Inc.
InventorsPatrick Chuang, Chao-Hung Chang, Lee-Lean Shu
Life of this patent
Estimating the term…
Abstract
A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.
Claims18
A memory computation cell, comprising:
- a storage cell having at least one storage PMOS transistor;
- at least one read bit line coupled to the storage cell through a read port wherein the read port buffers the storage cell from signals on the at least one read bit line and wherein the read bit line is configured to provide read access to a piece of data stored in the storage cell;
- wherein the memory computation cell is capable of performing a logic function when the memory computation cell is connected to the at least one read bit line with at least one other memory cell and the read bit line result in the logic function of 2 or more cells;
- and
- a ratioless write port coupled to the storage cell that provides write access to the storage cell, the ratioless write port permitting data to be written into the storage cell without overcoming a drive strength of the storage PMOS transistor.
2 more elements
A processing array, comprising:
- a plurality of memory cells arranged in an array, wherein each memory cell has a storage cell with at least one storage PMOS transistor, a read port for reading data from the storage cell and a write port for writing data to the storage cell, wherein the read port buffers the storage cell from signals on at least one read bit line and wherein the read bit line is configured to provide read access to a piece of data stored in the storage cell;
- a word line generator that is coupled to a read word line signal and a write word line signal for each memory cell in the array;
- a plurality of bit line read and write logic circuits that are coupled to the read bit line, write bit line and a complementary write bit line of each memory cell;
- each memory cell being coupled to a write word line and a read word line whose signals are generated by the word line generator and also being coupled to a read bit line, a write bit line and a complementary write bit line that are sensed by one of the plurality of bit line read and write logic circuits;
- the write port being a ratioless write port that provides write access to the storage cell, the ratioless write port permitting data to be written into the storage cell without overcoming a drive strength of the at least one storage PMOS transistor;
- and
- wherein two or more of the memory cells are coupled to at least one read bit line and activated to perform one of a Boolean operations.
4 more elements
A method for write operation in a computational memory cell, the method comprising:
- activating a write word line coupled to a computational memory cell in order to write a piece of data to a storage cell of the computational memory cell, the storage cell having at least one storage PMOS transistor;
- activating either of a write bit line or a complementary write bit line coupled to the computing memory cell;
- turning off a transistor whose gate is coupled to either of the write bit line or the complementary write bit line that is in turn connected to the at least one storage PMOS transistor;
- and
- performing a write operation into the storage cell without overcoming a drive strength of the at least one storage PMOS transistor.
2 more elements
Dependencies are inferred from the claim text.