US 10,854,283 B2 · Memory device with enhanced access capability and associated method

Abstract

A memory array includes a first memory cell and a second memory cell. Each of the first and the second memory cells includes a data storage element having a first terminal and a second terminal, a first access transistor coupled to the first terminal of the data storage element, and a second access transistor coupled to the second terminal of the data storage element. The memory array also includes a first word line and a second word line coupled to the first access transistor and the second access transistor, respectively, of the first memory cell, wherein the first word line and the second word line are operated independently during a read operation and activated at the same time during a write operation. The memory array further includes a first bit line coupled to the first access transistor of the first memory cell, a second bit line coupled to the second access transistor of the first memory cell, a third bit line coupled to the first access transistor of the second memory cell, and a first sense amplifier coupled to the first bit line and the third bit line.

Claims20

Dependent claims

A memory array, comprising:

a first memory cell and a second memory cell, each comprising:
a data storage element having a first terminal and a second terminal;
a first access transistor coupled to the first terminal of the data storage element;
and
a second access transistor coupled to the second terminal of the data storage element;
a first word line and a second word line coupled to the first access transistor and the second access transistor, respectively, of the first memory cell, wherein the first word line and the second word line are operated independently during a read operation and activated at the same time during a write operation;
a first bit line coupled to the first access transistor of the first memory cell;
a second bit line coupled to the second access transistor of the first memory cell;
a third bit line coupled to the first access transistor of the second memory cell;
a fourth bit line coupled to the second access transistor of the second memory cell;
a first sense amplifier coupled to the first bit line and the third bit line;
and
a second sense amplifier coupled to the second bit line and the fourth bit line.

10 more elements

A memory array, comprising:

a first plurality of memory cells and a second plurality of memory cells, wherein each memory cell of the first plurality of memory cells and the second plurality of memory cells comprises:
a data storage element having a first terminal and a second terminal;
and
a first access transistor and a second access transistor coupled to the first terminal and the second terminal, respectively;
a first word line and a second word line respectively coupled to the first access transistor and the second access transistor of one of the first plurality of memory cells;
a first bit line coupled to the first access transistor of each of the first plurality of memory cells;
a second bit line coupled to the second access transistor of each of the first plurality of memory cells;
a third bit line coupled to the first access transistor of each of the second plurality of memory cells;
a fourth bit line coupled to the second access transistor of each of the second plurality of memory cells;
a first sense amplifier coupled to the first bit line and the third bit line;
and
a second sense amplifier coupled to the second bit line and the fourth bit line.

9 more elements

A method of operating a memory array, the memory array comprising:

a first memory cell and a second memory cell, wherein each of the first memory cell and the second memory cell comprises:
a data storage element having a first terminal and a second terminal;
a first access transistor coupled to the first terminal;
and
a second access transistor coupled to the second terminal;
a first word line coupled to the first access transistor of the first memory cell;
a second word line coupled to the second access transistor of the first memory cell;
a first bit line coupled to the first access transistor of the first memory cell;
a second bit line coupled to the second access transistor of the first memory cell;
a third bit line coupled to the first access transistor of the second memory cell;
a fourth bit line coupled to the second access transistor of the second memory cell;
a first sense amplifier coupled to the first bit line and the third bit line;
and
a second sense amplifier coupled to the second bit line and the fourth bit line,
wherein the method comprises:
pulling a voltage level of the first bit line and a voltage level of the third bit line to a first voltage level;
asserting the first word line to turn on the first access transistor of the first memory cell and pull the voltage level of the first bit line to a second voltage level;
and
comparing the second voltage level to the first voltage level using the first sensing amplifier.

16 more elements

Dependencies are inferred from the claim text.

Memory device with enhanced access capability and associated method

Life of this patent

Memory device with enhanced access capability and associated method

Life of this patent

Abstract

Claims20