Memory read stability enhancement with short segmented bit line architecture

A semiconductor memory device comprising:

• a first conductive line extending over a first segment of memory cells in a memory array;
• a second conductive line extending over a second segment of memory cells in the memory array;
• a switch arranged between the first and second segments of memory cells and being configured to transition from an open state to a closed state to couple the first conductive line in series with the second conductive line;
• and
• a first write circuit coupled to the second conductive line, the first write circuit configured to apply a bias to the second conductive line while the switch is in the open state to write data to the second segment of memory cells.

A semiconductor memory device comprising:

• a first conductive line extending over a first segment of memory cells in a memory array, the first conductive line coupled to multiple memory cells within the first segment of memory cells;
• a second conductive line 402 extending over a second segment of memory cells and generally in parallel with the first conductive line, the second conductive line isolated from the memory cells of the second segment;
• and
• a switch 106 arranged between the first and second segments of memory cells, and configured to transition from an open state to a closed state to couple the first conductive line in series with the second conductive line;
• and
• wherein the semiconductor memory device is configured to develop a bias on the first conductive line when the switch is in the open state, the bias corresponding to a data state read from at least one memory cell in the first segment when the switch is in the open state.