Read assist circuitry for memory applications

An integrated circuit, comprising:

• a wordline driver coupled to a bitcell via a first wordline;
• and
• a read assist transistor coupled to the first wordline between the wordline driver and the bitcell, wherein the read assist transistor is controlled based on an analog activation signal,
• wherein, while activated, the read assist transistor generates an underdrive on the first wordline when the first wordline is selected and driven by the wordline driver,
• wherein the read assist transistor is coupled to the first wordline at a first node between the wordline driver and the bitcell, and wherein the read assist transistor is also coupled to a plurality of other wordlines.

An integrated circuit, comprising:

• a wordline driver coupled to a bitcell via a wordline;
• a read assist transistor coupled to the wordline between the wordline driver and the bitcell;
• and
• a first transistor coupled between a gate of the read assist transistor and a negative voltage supply (Vss),
• wherein, while activated, the first transistor is activated with an activation signal provided by the wordline,
• wherein, while activated, the read assist transistor generates an underdrive on the wordline when the wordline is selected and driven by the wordline driver,
• wherein the read assist transistor is activated with a read assist signal provided by a second transistor coupled as a diode between a positive voltage supply (Vdd) and the gate of the read assist transistor, and
• wherein a gate of the first transistor receives the activation signal from the wordline at a node disposed before the wordline driver, and wherein the first transistor allows the second transistor that is coupled as a diode to provide the read assist signal to the read assist transistor when the wordline is selected.

An integrated circuit, comprising:

• a dummy wordline driver coupled to a dummy load via a dummy wordline;
• and
• multiple read assist transistors coupled in series between a first node on the dummy wordline between the dummy wordline driver and the dummy load and a second node connected to a negative voltage supply (Vss),
• wherein gates of the multiple read assist transistors are connected to an activation signal, wherein the activation signal is provided by a positive voltage supply (Vdd), and
• wherein the multiple read assist transistors are activated with a read assist signal, and while activated, the multiple read assist transistors generate an underdrive on the dummy wordline to delay a rising edge of a wordline signal that is provided by the dummy wordline driver on the dummy wordline.

A method for manufacturing an integrated circuit, the method comprising:

• fabricating a wordline driver coupled to a bitcell via a wordline;
• fabricating a read assist transistor coupled to the wordline between the wordline driver and the bitcell, wherein the read assist transistor is activated with a read assist signal, and while activated, the read assist transistor generates an underdrive on the wordline when the wordline is selected and driven by the wordline driver;
• and
• fabricating a read assist activation circuit having multiple transistors arranged to receive a single activation signal and provide the read assist signal to a gate of the read assist transistor based on the single activation signal, wherein the single activation signal controls the read assist transistor based on an analog voltage.