SRAM structure with reduced capacitance and resistance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad.
Claims20
An integrated circuit structure comprising:
- a Static Random Access Memory (SRAM) cell comprising:
- a first pull-up Metal-Oxide Semiconductor (MOS) device and a second pull-up MOS device;
- and
- a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device;
- a first CVss landing pad electrically coupling to a source of the first pull-down MOS device, wherein the first CVss landing pad has a portion in the SRAM cell, with the portion having a first length and a first width smaller than a second length and a second width, respectively, of the SRAM cell;
- and
- a first word-line having a first lengthwise direction, wherein the first word-line extends from a first boundary of the SRAM cell to a second boundary of the SRAM, with the first boundary and the second boundary being parallel to each other, and wherein the first word-line and the first CVss landing pad are in a same metal layer.
An integrated circuit structure comprising:
- a Static Random Access Memory (SRAM) cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell comprising:
- a first pull-up Metal-Oxide Semiconductor (MOS) device and a second pull-up MOS device;
- and
- a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device;
- and
- a word-line extending from the first boundary to the second boundary, wherein the word-line comprises:
- a strip portion in the SRAM cell, the strip portion having a rectangular top-view shape, wherein the strip portion extends from the first boundary to the second boundary;
- and
- a first jog portion joining a first sidewall of the strip portion, wherein the first jog portion extends to the first boundary, and the first jog portion is spaced apart from the second boundary.
An integrated circuit structure comprising:
- a Static Random Access Memory (SRAM) cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, wherein the third boundary and the fourth boundary are perpendicular to the first boundary and the second boundary;
- a first CVss landing pad over and electrically coupling to the SRAM cell;
- and
- a second CVss landing pad overlapping and electrically connected to the first CVss landing pad, wherein each of the first CVss landing pad and the second CVss landing pad extends to both of the first boundary and the fourth boundary, and is spaced apart from the second boundary and the third boundary.
Dependencies are inferred from the claim text.