Sense amplifier for sensing multi-level cell and memory device including the sense amplifer

A method of sensing multi-bit memory cell data, the method comprising:

• precharging a bit line pair, a first sensing bit line pair, and a second sensing bit line pair to a precharge voltage having a half of a level of a power voltage, the bit line pair including a bit line and a complementary bit line, the first sensing bit line pair including a first sensing bit line and a first complementary sensing bit line, the second sensing bit line pair including a second sensing bit line and a second complementary sensing bit line, the bit line being connected to a memory cell, and the memory cell storing a cell voltage of 2-bit data;
• performing an offset cancelling operation, the offset cancelling operation decreasing a voltage difference between the bit line and the complementary bit line;
• performing a first charge sharing operation, the first charge sharing operation occurring between a charge of the memory cell and a charge of the bit line;
• sensing a most significant bit (MSB) of the 2-bit data of the memory cell and latching the MSB of the 2-bit data into the first sensing bit line pair;
• performing a symmetrical connection operation, the symmetrical connection operation connecting the first sensing bit line and the second complementary sensing bit line and connecting the first complementary sensing bit line and the second sensing bit line;
• performing a second charge sharing operation, the second charge sharing operation sharing charge between a charge of the bit line and a charge of the first complementary sensing bit line, and sharing charge between a charge of the complementary bit line and a charge of the first sensing bit line;
• sensing a least significant bit (LSB) of the 2-bit data and latching the LSB of the 2-bit data into the second sensing bit line pair;
• performing a third charge sharing operation, the third charge sharing operation occurring between a charge of the bit line pair and a charge of the first sensing bit line pair;
• and
• rewriting the cell voltage corresponding to sensed MSB and LSB of the 2-bit data to the memory cell.

A system comprising:

• a processing unit;
• and
• a first memory device coupled to the processing unit, the first memory device including a plurality of first memory cells and a plurality of sense amplifiers, each of the plurality of first memory cells storing a cell voltage of 2-bit data,
• wherein each of the plurality of sense amplifiers comprises:
• a first sense amplification circuit connected between a bit line and a complementary bit line, the bit line being connected to the each of the plurality of first memory cells, the first sense amplification circuit being configured to sense a least significant bit (LSB) of the 2-bit data and latch the LSB of the 2-bit data in a first sensing bit line pair, and the first sensing bit line pair including a first sensing bit line and a first complementary sensing bit line;
• a second sense amplification circuit configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB of the 2-bit data in a second sensing bit line pair, and the second sensing bit line pair including a second sensing bit line and a second complementary sensing bit line;
• and
• a switching circuit configured to selectively connect between the bit line, the complementary bit line, the first sensing bit line, the first complementary sensing bit line, the second sensing bit line, and the second complementary sensing bit line.