Memory device and operation method thereof

An operation method of a memory device, the memory device including a plurality of memory cells connected to a plurality of word lines, the method comprising:

• receiving an activate command from an external source;
• receiving at least one operation command from the external source;
• receiving a precharge command from the external source;
• determining whether the at least one operation command includes a write command;
• receiving an additional active command from the external source;
• in response to the results of the determining indication the at least one operation command does not include the write command, receiving the additional activate command after a first precharge reference time period elapses, the first precharge reference time period starting from a time when the precharge command is received;
• and
• in response to the results of the determining indicating the at least one operation command includes the write command, receiving the additional activate command after a second precharge reference time period longer than the first precharge reference time period elapses, the second precharge reference time period starting from the time at which the precharge command is received, and
• writing write data corresponding to the write command to selection memory cells connected to a selection word line among the plurality of word lines after receiving the precharge command.

A memory device comprising:

• a memory cell array including a plurality of dynamic random access memory (DRAM) cells connected to a plurality of word lines and a plurality of bit lines;
• a row decoder configured to select a selection word line among the plurality of word lines based on a row address from an external source;
• a column decoder configured to select a selection bit line among the plurality of bit lines based on a column address from the external source;
• an input/output circuit connected to the plurality of bit lines and configured to exchange data with the external source;
• a command decoder configured to decode an activate command, at least one operation command, and a precharge command received from the external source;
• a write command detector circuit configured to detect a write command from the at least one operation command based on a decoding result of the command decoder;
• and
• a control logic circuit configured to,
• activate the selection word line in response to the activate command,
• in response to the write command not being detected, receive an additional activate command after a first precharge reference time period elapses, the first precharge reference time period starting from a time when the precharge command is received;
• and
• in response to the write command being detected, the control logic circuit is further configured to receive the additional activate command after a seond precharge reference time period longer than the first precharge reference time period elapses, the second precharge reference time period starting from the time at which the precharge command is received, and
• write write data corresponding to the write command to selection memory cells from among the plurality of DRAM memory cells, the selection memory cells being connected to the selection word line, after receiving the precharge command.