US 10,854,270 B2 · Memory with internal refresh rate control

Abstract

Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines.

Claims25

Dependent claims

A memory device, comprising:

a memory array including a plurality of word lines arranged in a plurality of memory banks, wherein the plurality of word lines include main word lines and redundant word lines;
and
circuitry configured to:
store a pump value indicating a current pump in a pump sequence,
store a multi-bit value indicating one or more addresses corresponding to one or more word lines in the plurality of word lines,
compress at least one bit of the multi-bit value such that the compressed multi-bit value simultaneously indicates more than one address corresponding to more than one word line in the plurality of word lines,
disable redundancy match,
activate the main word lines separate from the redundant word lines by firing a first pump in accordance with the pump sequence to activate, in parallel, the more than one word line corresponding to the more than one address simultaneously indicated by the compressed, multi-bit value to refresh data stored in the memory array, and
update the multi-bit value based at least in part on activating the more than one word line.

6 more elements

A method for refreshing data stored in a memory device, the method comprising:

storing a value indicating a current pump in a pump sequence;
storing a multi-bit value indicating one or more addresses corresponding to one or more word lines in a plurality of word lines of the memory device, wherein the plurality of word lines are arranged in a plurality of memory banks in a memory array of the memory device;
compressing at least one bit of the multi-bit value such that the multi-bit value simultaneously indicates more than one address corresponding to more than one word line of the plurality of word lines;
disabling redundancy match;
activating main word lines in the plurality of word lines separate from redundant word lines in the plurality of word lines by firing a first pump in accordance with the pump sequence to activate, in parallel, the more than one word line corresponding to the more than one address simultaneously indicated by the compressed, multi-bit value, wherein the more than one word line is activated to refresh data stored in the memory device;
and
updating the multi-bit value based at least in part on activating the more than one word line.

4 more elements

Dependencies are inferred from the claim text.

Memory with internal refresh rate control

Life of this patent

Memory with internal refresh rate control

Life of this patent

Abstract

Claims25