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US 10,854,265 B2Granted
Time tracking circuit for FRAM
AssigneeTexas Instruments Incorporated
InventorDavid J. Toops
Life of this patent
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Abstract
An example memory circuit for reading and/or writing FRAM memory includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.
Claims20
A system comprising:
- a memory circuit comprising:
- a ferroelectric random access memory (FRAM) array comprising:
- a plurality of bit cells, each of the plurality of bit cells including at least one ferroelectric capacitor;
- a set of word line inputs coupled to the plurality of bit cells;
- and
- a set of plate line inputs coupled to the ferroelectric capacitors of the plurality of bit cells, wherein the FRAM array has a minimum amount of delay between assertion of a word line signal on the set of word line inputs and assertion of a plate line signal on the set of plate line inputs to enable a read of or a write to respective ones of the plurality of bit cells, the minimum amount of delay based on a number of bit cell columns in the FRAM array;
- a controller that includes a plate line driver output to provide a first driver signal a first delay after assertion of the word line signal, wherein the controller includes a timing circuit to generate the first driver signal after the first delay;
- a plate line driver that includes an input coupled to the plate line driver output of the controller to receive the first driver signal and a set of outputs to provide a set of plate line control signals in response to the first driver signal;
- and
- a set of transistors coupled to the set of outputs of the plate line driver and to the set of plate line inputs of the FRAM array, wherein each transistor of the set of transistors includes:
- a gate terminal coupled to a respective output of the set of outputs of the plate line driver;
- a second terminal coupled to a respective plate line input of the set of plate line inputs of the FRAM array;
- and
- a third terminal coupled to a voltage source, wherein each transistor of the set of transistors is configured to have a transistor delay such that a respective plate line control signal is received at the gate terminal at a second delay that is less than the minimum amount of delay after assertion of the word line signal and the transistor provides a plate line signal to the respective plate line input of the set of plate line inputs of the FRAM array at least the minimum amount of delay after assertion of the word line signal.
11 more elements
A memory circuit comprising:
- a capacitive memory array that includes:
- a plurality of cells that each include a respective capacitor;
- a set of word line inputs coupled to the plurality of cells;
- and
- a set of plate line inputs coupled to the capacitors of the plurality of cells;
- a controller that includes a plate line driver output to provide a first driver signal;
- a plate line driver that includes an input coupled to the plate line driver output of the controller to receive the first driver signal and a set of outputs to provide a set of plate line control signals;
- a set of transistors coupled to the set of outputs of the plate line driver and to the set of plate line inputs of the capacitive memory array, wherein:
- each of the set of transistors is configured to provide a voltage to a respective plate line input of the set of plate line inputs of the capacitive memory array in response to a respective plate line control signal of the set of plate line control signals;
- and
- each of the set of transistors has a delay such that the respective transistor is configured to receive the respective plate line control signal at a first time that is less than a minimum amount of plate line delay after assertion of a signal at a respective word line input of the set of word line inputs and to provide the voltage to the respective plate line input at a second time that is at least the minimum amount of plate line delay after assertion of the signal at the respective word line input;
- wherein the minimum amount of plate line delay is a minimum delay to enable a read of or a write to respective ones of the plurality of cells.
9 more elements
A device comprising:
- a capacitive memory controller that includes a word line output, a bit line output, and a plate line output;
- a row driver that includes an input coupled to the word line output of the capacitive memory controller and a set of outputs to provide a set of word line control signals;
- a bit line driver that includes an input coupled to the bit line output of the capacitive memory controller and a set of outputs to provide a set of bit line control signals;
- a first set of transistors coupled to the set of outputs of the bit line driver and configured to provide a set of bit line signals at a set of bit lines of a capacitive memory array;
- a plate line driver that includes an input coupled to the plate line output of the capacitive memory controller and a set of outputs to provide a set of plate line control signals;
- and
- a second set of transistors coupled to the set of outputs of the plate line driver and configured to provide a set of plate line signals at a set of plate lines of the capacitive memory array, wherein:
- the capacitive memory controller and the bit line driver are configured to provide the set of bit line control signals to the first set of transistors at a first time that is less than a minimum bit line delay of the capacitive memory array;
- and
- the first set of transistors are configured to provide the set of bit line signals at a second time that is at least the minimum bit line delay of the capacitive memory array;
- wherein the minimum bit line delay is a minimum amount of delay between assertion of a word line control signal on the row driver outputs and assertion of a bit line control signal on the bit driver outputs to enable a read of or a write to the capacitive memory array.
8 more elements
Dependencies are inferred from the claim text.