Current-starved delay circuitry
AssigneeArm Limited
InventorsSurya Prakash Gupta, Piyush Jain, El Mehdi Boujamaa
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Abstract
Various implementations described herein refer to an integrated circuit having a sense amplifier that operates with a clock signal, and the sense amplifier may be biased with a bias signal that affects duration of the clock signal. The integrated circuit may include a delay circuit coupled to the sense amplifier, and the delay circuit may turn-off the clock signal. The delay circuit may have a current-starved delay stage that receives an input signal having a falling edge and provides a current-starved delay signal biased by the bias signal that also biases the sense amplifier.
Claims20
An integrated circuit, comprising:
- a sense amplifier that operates with a clock signal, wherein the sense amplifier is biased with a bias signal that affects duration of the clock signal;
- and
- a delay circuit coupled to the sense amplifier, wherein the delay circuit turns-off the clock signal, and wherein the delay circuit has a current-starved delay stage that receives an input signal having a falling edge and provides a current-starved delay signal biased by the bias signal that also biases the sense amplifier.
An integrated circuit, comprising:
- a sense amplifier configured to operate with a clock signal;
- an input delay circuit having an input inverter that receives an input signal and provides a delayed inversion signal;
- a current-starved delay circuit having a first inverter delay chain coupled to the input inverter, wherein the first inverter delay chain receives the delayed inversion signal from the input inverter and provides a current-starved delay signal;
- an output delay circuit having a second inverter delay chain arranged to operate as an output buffer that receives the current-starved delay signal from the first inverter delay chain and provides a delayed current-starved delay signal as an output signal;
- and
- logic circuitry configured to generate the clock signal based on the output signal.
An integrated circuit, comprising:
- an input delay circuit having an input inverter that receives an input signal and provides a delayed inversion signal;
- a current-starved delay circuit having a first inverter delay chain coupled to the input inverter, wherein the first inverter delay chain receives the delayed inversion signal from the input inverter and provides a current-starved delay signal;
- and
- an output delay circuit having a second inverter delay chain arranged to operate as an output buffer that receives the current-starved delay signal from the first inverter delay chain and provides a delayed current-starved delay signal as an output signal;
- wherein:
- the first inverter delay chain includes a first inverter that receives the delayed inversion signal from the input inverter as a first inversion signal, receives a first supply voltage via a first pass transistor, generates a second inversion signal based on the first supply voltage, and provides the second inversion signal to a first node, and
- the first pass transistor is coupled between the first supply voltage and a power supply connection of the first inverter, wherein the first pass transistor is activated with a voltage bias signal, and wherein the first pass transistor provides the first supply voltage to the power supply connection of the first inverter when activated.
A method, comprising:
- fabricating a sense amplifier configured to operate with a clock signal;
- fabricating input delay circuitry that receives an input signal and provides a delayed inversion signal;
- fabricating current-starved delay circuitry as an inverter delay chain that receives the delayed inversion signal from the input delay circuitry and provides a current-starved delay signal based on the delayed inversion signal;
- fabricating output buffer circuitry that receives the current-starved delay signal from the current-starved delay circuit and provides a delayed current-starved delay signal as an output signal;
- and
- fabricating logic circuitry configured to generate the clock signal based on the output signal.
Dependencies are inferred from the claim text.