Memory device
AssigneeSamsung Electronics Co., Ltd.
InventorSang-Hoon Jung
Life of this patent
Estimating the term…
Abstract
A memory device includes a first memory cell that is connected with a first source line, a first word line, and a first bit line, a first write circuit to receive first write data that are stored in the first memory cell through a first write input/output line and to control a voltage of the first source line and a voltage of the first bit line based on the first write data, and a first pull-down circuit to receive first pull-down data corresponding to the first write data from the first write circuit through a first internal metal line and to pulls down the voltage of at least one of the first source line and the first bit line to a predetermined voltage based on the first pull-down data.
Claims20
A memory device comprising:
- a first memory cell connected with a first source line, a first word line, and a first bit line;
- a first write circuit to receive first write data through a first write input/output line, the first write data to be stored in the first memory cell, and to control a voltage of the first source line and a voltage of the first bit line based on the first write data;
- and
- a first pull-down circuit to receive first pull-down data corresponding to the first write data from the first write circuit through a first internal metal line, and to pull down the voltage of one of the first source line and the first bit line to a predetermined voltage based on the first pull-down data.
A memory device, comprising:
- a first sub memory cell array including first memory cells that are respectively connected with a plurality of word lines;
- a second sub memory cell array including second memory cells that are respectively connected with the plurality of word lines;
- a dummy area between the first and second sub memory cell arrays, a first internal metal line and a second internal metal line being in the dummy area;
- a first write circuit to control a voltage of a first bit line and a voltage of a first source line based on first write data received through a first write input/output line, the first bit line and the first source line being connected with the first memory cells;
- a first pull-down circuit to receive first pull-down data corresponding to the first write data from the first write circuit through the first internal metal line and to pull down the voltage of the first source line or the voltage of the first bit line to a first predetermined voltage based on the first pull-down data;
- a second write circuit to control a voltage of a second bit line and a voltage of a second source line based on second write data that are received through a second write input/output line, the second bit line and the second source line being connected with the second memory cells;
- and
- a second pull-down circuit to receive second pull-down data corresponding to the second write data from the second write circuit through the second internal metal line and to pull down the voltage of the second source line or the voltage of the second bit line to a second predetermined voltage based on the second pull-down data.
A memory device, comprising:
- a memory cell array in a core area of a semiconductor substrate, the memory cell array including a plurality of memory cells connected to a plurality of word lines;
- a write driver in a peripheral area of the semiconductor substrate, the write driver to control voltages of a plurality of bit lines and voltages of a plurality of source lines based on first write data that are received through write input/output lines, the plurality of bit lines and the plurality of source lines being connected with the plurality of memory cells;
- and
- a pull-down driver to receive first pull-down data corresponding to the first write data from the write driver through at least one internal metal line and to pull down the voltages of the plurality of bit lines or the voltages of the plurality of source lines to a predetermined voltage based on the first pull-down data,
- wherein the at least one internal metal line crosses the core area and extends from the write driver to the pull-down driver.
Dependencies are inferred from the claim text.