Vertical selector stt-MRAM architecture

A memory array, comprising:

• an electrically conductive source-plane;
• an array of vertical semiconductor channel structures;
• and
• a plurality of memory elements, each of the memory elements being electrically connected one of the vertical semiconductor channel structures;
• wherein
• the vertical semiconductor channel structures are formed on and connected with the source-plane in two dimensions;
• wherein each of the vertical semiconductor channel structures includes a semiconductor column structure and a gate dielectric layer surrounding the semiconductor column structure, wherein the semiconductor column structure is formed by selective epitaxial growth.

A memory array, comprising;

• a two-dimensional array of channel selectors arranged in rows and columns;
• a two-dimensional source-plane electrically connected with the two-dimensional array of channel selectors in both the row and column direction;
• and
• a plurality of memory element structures formed on the two-dimensional array of channel selectors, wherein the memory element structures are two terminal resistive switching memory elements;
• wherein the channel structures include a semiconductor formed by selective epaxial growth.