Memory device including a circuit for detecting word line defect and operating method thereof

A method for operating a memory device, the method comprising:

• providing a memory cell array including a first memory cell disposed on a substrate, a first word line connected to the first memory cell, a second memory cell disposed above the first memory cell, and a second word line disposed above the first word line and connected to the second memory cell;
• generating a pumping clock signal when a pumping voltage is lower than a reference pumping voltage;
• generating the pumping voltage responsive to the pumping clock signal, a first voltage based on the pumping voltage, and a second voltage different from the first voltage;
• detecting a defect of the first word line by monitoring a first number of pulses of the pumping clock signal while applying the first voltage to the first word line;
• when the first number of pulses of the pumping clock signal is smaller than a first reference value, programming the second memory cell by applying the second voltage to the second word line, and
• applying the second voltage to the first word line for programming the first memory cell after the programming of the second memory cell is completed.

A memory device comprising:

• a memory cell array including a first memory cell disposed on a substrate, a second memory cell disposed above the first memory cell, and a third memory cell disposed above the second memory cell;
• a first word line connected to the first memory cell, a second word line connected to the second memory cell, and a third word line connected to the third memory cell, the second word line disposed above the first word line, the third word line disposed above the second word line;
• a clock generator configured to generate a pumping clock signal when a pumping voltage is lower than a reference pumping voltage;
• a voltage generator configured to generate the pumping voltage responsive to the pumping clock signal, and generate a first program voltage based on the pumping voltage and a second program voltage different from the first program voltage;
• and
• a word line defect detection circuit configured to monitor a first number of pulses of the pumping clock signal while applying the first program voltage to the first word line to detect a defect of the first word line,
• wherein, when the first number of pulses of the pumping clock signal is smaller than a first reference value, the word line defect detection circuit is configured to monitor a second number of pulses of the pumping clock signal while applying the first program voltage to the second word line to detect a defect of the second word line, and
• wherein the voltage generator is configured to apply the second program voltage to the third word line for programming the third memory cell when the second number of pulses of the pumping clock signal is smaller than the first reference value.