Data and clock synchronization and variation compensation apparatus and method

An apparatus comprising:

• a first circuitry to adjust one or more signal characteristics of an input clock, and to provide first and second clocks;
• a first transmitter to sample data, for transmission, with a version of the first clock and to transmit the sampled data to a first receiver;
• and
• a second transmitter to transmit the second clock to a second receiver, wherein the first receiver and the second receiver are in a different die than a die comprising the first transmitter and the second transmitter.

A system-on-chip comprising:

• a memory;
• a first die coupled to the memory;
• a second die coupled to the first die;
• and
• a communication interface to allow the first and/or second dies to communicate with another device, wherein the first die includes:
• a first adjustable buffer to receive an input clock and provide a first clock;
• a second adjustable buffer to receive the input clock and provide a second clock, wherein the first and second adjustable buffers are to modify one or more signal characteristics of the first and the second clocks, respectively, according to one or more controls;
• a first transmitter to sample data with a delayed version of the first clock, and to transmit the sampled data to a first receiver;
• and
• a second transmitter to transmit the second clock to a second receiver.