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US 10,854,246 B1Granted
Memory with high-speed and area-efficient read path
AssigneeQUALCOMM Incorporated
InventorsAdithya Bhaskaran, Mukund Narasimhan, Shiba Narayan Mohanty
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Abstract
A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.
Claims17
A read path for a memory, comprising:
- a sense amplifier;
- a data latch;
- a first transistor coupled between a first output node of the sense amplifier and a first input node to the data latch;
- and
- a first logic gate configured to assert a combined sense enable and redundancy shift-off signal in response to an assertion of both a sense enable signal and a redundancy shift-off signal, wherein the first transistor is configured to switch on in response to the assertion of the combined sense enable and redundancy shift-off signal.
2 more elements
A method of operation for a memory read path, comprising:
- switching on a first transistor in response to an assertion of both a sense enable signal and a redundancy shift-off signal;
- driving a first bit decision signal through the switched-on first transistor from a sense amplifier to a data latch;
- and
- latching the first bit decision signal in the data latch.
1 more element
Dependencies are inferred from the claim text.