Coarse compute shading
AssigneeIntel Corporation
InventorJohn Gierach
Life of this patent
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Abstract
Embodiments described herein provide an apparatus comprising a processor to maintain a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse selection dispatch rate, receive a request message to dispatch coarse compute shader work, the request message comprising a requested coarse selection dispatch rate and a thread identifier, and store the request message in a FIFO queue structure having a coarse selection dispatch rate corresponding to the requested coarse selection dispatch rate associated with the request message. Other embodiments may be described and claimed.
Claims11
A method, comprising:
- maintaining a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse rate version of a course compute shader executed in a graphics processing device;
- receiving a request message to dispatch coarse compute shader work of the coarse compute shader, the request message comprising a requested level of coarseness and a thread identifier;
- storing the request message in a FIFO queue structure of the plurality of FIFO queue structures having the coarse rate version corresponding to the requested level of coarseness associated with the request message;
- generating a message with instructions to dispatch a compute shader thread having a coarseness level corresponding to the level of coarseness of the FIFO queue structure in response to a determination that a watchdog timer expired before the FIFO queue structure comprises a number of request messages sufficient to dispatch the coarse compute shader work with a fully populated single instruction multiple data (SIMD) thread;
- forwarding the message to a thread dispatcher;
- and
- releasing data in the FIFO queue structure with the message to the thread dispatcher.
A non-transitory machine readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations comprising:
- maintaining a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse rate version of a course compute shader executed in a graphics processing device;
- receiving a request message to dispatch coarse compute shader work of the coarse compute shader, the request message comprising a requested level of coarseness and a thread identifier;
- storing the request message in a FIFO queue structure of the plurality of FIFO queue structures having the coarse rate version corresponding to the requested level of coarseness associated with the request message;
- generating a message with instructions to dispatch a compute shader thread having a coarseness level corresponding to the level of coarseness of the FIFO queue structure in response to a determination that a watchdog timer expired before the FIFO queue structure comprises a number of request messages sufficient to dispatch the coarse compute shader work with a fully populated single instruction multiple data (SIMD) thread;
- forwarding the message to a thread dispatcher;
- and
- releasing data in the FIFO queue structure with the message to the thread dispatcher.
An apparatus, comprising:
- a processor to:
- maintain a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse rate version of a course compute shader executed in a graphics processing device;
- receive a request message to dispatch coarse compute shader work of the coarse compute shader, the request message comprising a requested level of coarseness and a thread identifier;
- and
- store the request message in a FIFO queue structure of the plurality of FIFO queue structures having the coarse rate version corresponding to the requested level of coarseness associated with the request message;
- generate a message with instructions to dispatch a compute shader thread having a coarseness level corresponding to the level of coarseness of the FIFO queue structure in response to a determination that a watchdog timer expired before the FIFO queue structure comprises a number of request messages sufficient to dispatch the coarse compute shader work with a fully populated single instruction multiple data (SIMD) thread;
- forward the message to a thread dispatcher;
- and
- release data in the FIFO queue structure with the message to the thread dispatcher;
- and
- a memory communicatively coupled to the processor.
Dependencies are inferred from the claim text.