US 10,853,904 B2Granted

Hierarchical register file at a graphics processing unit

AssigneeAdvanced Micro Devices, Inc.

InventorsYasuko Eckert, Nuwan Jayasena

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Abstract

A processor employs a hierarchical register file for a graphics processing unit (GPU). A top level of the hierarchical register file is stored at a local memory of the GPU (e.g., a memory on the same integrated circuit die as the GPU). Lower levels of the hierarchical register file are stored at a different, larger memory, such as a remote memory located on a different die than the GPU. A register file control module monitors the status of in-flight wavefronts at the GPU, and in particular whether each in-flight wavefront is active, predicted to be become active, or inactive. The register file control module places execution data for active and predicted-active wavefronts in the top level of the hierarchical register file and places execution data for inactive wavefronts at lower levels of the hierarchical register file.

Claims20

Dependent claims

A processing system comprising:

a processor to couple to a first memory implementing a first register file and to couple to a second memory implementing a second register file, the processor comprising:
a graphics processing unit (GPU) to execute a plurality of wavefronts, the GPU comprising an active wavefront predictor coupled to an inactive wavefront detector, GPU configured, in response to identifying a wavefront activity status for at least one of the wavefronts, to perform at least one of:
when the wavefront activity status is identified as an active wavefront ready for execution at the GPU, storing execution data for the at least one wavefront at the first register file;
when the wavefront activity status is identified, by the active wavefront predictor, as predicted to transition from an inactive wavefront to an active wavefront within a threshold number of clock cycles, transferring execution data for the at least one wavefront from the second register file to the first register file;
and
when the wavefront activity status is identified as an inactive wavefront awaiting execution based on the inactive wavefront detector detecting a high-latency instruction at an instruction pipeline of the processor, storing execution data for the at least one wavefront at the second register file.

3 more elements

A method comprising:

in response to a processor that has a first memory coupled to a second memory and a graphics processing unit (GPU) coupled to a register file control module, identifying, using the register file control module having an active wavefront predictor coupled to an inactive wavefront detector, a first wavefront of a plurality of wavefronts pending for execution at the GPU is an active wavefront, storing execution data for the first wavefront at a first register file implemented at the first memory;
in response to the active wavefront predictor predicting a second wavefront of the plurality of wavefronts is to transition from an inactive wavefront to an active wavefront within a threshold number of clock cycles, transferring execution data for the second wavefront from a second register file to the first register file at the first memory;
and
in response to the inactive wavefront detector identifying a third wavefront of the plurality of wavefronts is an inactive wavefront awaiting execution based on detecting a high-latency instruction at an instruction pipeline of the processor, storing execution data for the third wavefront at the second register file implemented at the second memory separate from the first memory.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 15/079,543Filed 24 Mar 2016
Published: US 2017/0278213 A128 Sep 2017
Granted: 1 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06T 1/20
General purpose image data processing: processor architectures; Processor configuration, e.g. pipelining
G06F 9/30123
Organisation of register space, e.g. banked or distributed register file: according to context, e.g. thread buffers
G06F 9/30138
Organisation of register space, e.g. banked or distributed register file: extension of register space, e.g. register cache
G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming