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US 10,853,722 B2Granted
Apparatus for executing LSTM neural network operation, and operational method
AssigneeSanghai Cambricon Information Technology Co., Ltd.
InventorsYunji Chen, Xiaobing Chen, Shaoli Liu, Tianshi Chen
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Abstract
Aspects of processing data for Long Short-Term Memory (LSTM) neural networks are described herein. The aspects may include one or more data buffer units configured to store previous output data at a previous timepoint, input data at a current timepoint, one or more weight values, and one more bias values. The aspects may further include multiple data processing units configured to parallelly calculate a portion of an output value at the current timepoint based on the previous output data at the previous timepoint, the input data at the current timepoint, the one or more weight values, and the one or more bias values.
Claims16
A Long Short-Term Memory (LSTM) neural network processor, comprising:
- one or more on-chip data buffer circuits configured to store previous output data at a previous timepoint, input data at a current timepoint, one or more weight values, and one more bias values,
- wherein the weight values include:
- one or more forget gate weight values corresponding to a forget gate,
- one or more input gate weight values corresponding to an input gate,
- one or more candidate weight values corresponding to an updated state cell, and
- one or more output gate weight values corresponding to an output gate, and
- wherein the bias values include:
- one or more forget gate bias values corresponding to the forget gate,
- one or more input gate bias values corresponding to the input gate,
- one or more candidate bias values corresponding to the candidate state value, and
- one or more output gate bias values corresponding to the output gate;
- and
- multiple data processing circuits configured to calculate an output value at the current timepoint based on the previous output data at the previous timepoint, the input data at the current timepoint, the one or more weight values, and the one or more bias values,
- wherein each of the multiple data processing circuits is configured to parallelly calculate a portion of the output value,
- wherein the multiple data processing circuits are configured to combine the portions of the output value into the output value at the current timepoint,
- wherein each of the multiple data processing circuits are configured to parallelly calculate a portion of a forget gate output based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more forget gate weight values, the one or more forget gate bias values,
- wherein each of the multiple data processing circuits are configured to parallelly calculate a portion of an input gate output based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more input gate weight values, and the one or more input gate bias values,
- wherein each of the multiple data processing circuits are configured to parallelly calculate a portion of a candidate state value based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more candidate weight values, and the one or more candidate bias values,
- wherein each of the multiple data processing circuits are configured to parallelly calculate a portion of an output gate value based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more output gate weight values, and the one or more output gate bias values,
- wherein each of the multiple data processing circuits are configured to parallelly calculate the updated state cell at the current timepoint based on a previous state value at the previous timepoint, the candidate state value, the forget gate output, and the input gate output, and
- wherein each of the multiple data processing circuits are configured to parallelly calculate the portion of the output value based on the output gate value and the updated state cell.
18 more elements
A method for processing data for Long Short-Term Memory (LSTM) neural networks, comprising:
- storing, by one or more on-chip data buffer circuits, previous output data at a previous timepoint, input data at a current timepoint, one or more weight values, and one more bias values,
- wherein the weight values include:
- one or more forget gate weight values corresponding to a forget gate,
- one or more input gate weight values corresponding to an input gate,
- one or more candidate weight values corresponding to an updated state cell, and
- one or more output gate weight values corresponding to an output gate, and
- wherein the bias values include:
- one or more forget gate bias values corresponding to the forget gate,
- one or more input gate bias values corresponding to the input gate,
- one or more candidate bias values corresponding to the candidate state value, and
- one or more output gate bias values corresponding to the output gate;
- parallelly calculating, by each of multiple data processing circuits, a portion of an output value at the current timepoint based on the previous output data at the previous timepoint, the input data at the current timepoint, the one or more weight values, and the one or more bias values;
- combining, by the multiple data processing circuits, the calculated portions of the output value into the output value at the current timepoint, and
- parallelly calculating, by each of the multiple data processing circuits, a portion of a forget gate output based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more forget gate weight values, the one or more forget gate bias values;
- parallelly calculating, by each of the multiple data processing circuits, a portion of an input gate output based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more input gate weight values, and the one or more input gate bias values;
- parallelly calculating, by each of the multiple data processing circuits, a portion of a candidate state value based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more candidate weight values, and the one or more candidate bias values;
- parallelly calculating, by each of the multiple data processing circuits, a portion of an output gate value based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more output gate weight values, and the one or more output gate bias values;
- parallelly calculating, by each of the multiple data processing circuits, the updated state cell at the current timepoint based on a previous state value at the previous timepoint, the candidate state value, the forget gate output, and the input gate output;
- and
- parallelly calculating, by each of the multiple data processing circuits, the portion of the output value based on the output gate value and the updated state cell.
17 more elements
Dependencies are inferred from the claim text.