Method for improving circuit layout for manufacturability

A method for manufacturing an integrated circuit (IC), comprising:

• receiving a layout of the IC having a first region interposed between two other regions, the first region and the two other regions oriented lengthwise along a first direction,
• wherein the layout includes a first layer having first features oriented lengthwise along a second direction perpendicular to the first direction, the first features traversing the first region and intersecting the two other regions,
• wherein the layout further includes a second layer having second features in the first region, the second features oriented lengthwise along the first direction,
• wherein the layout further includes a third layer having third features in the first region, the third features oriented lengthwise along the first direction,
• wherein the second and third features collectively form cut patterns for the first features;
• modifying the second and third features by a mask house tool,
• wherein the modifying of the second and third features includes:
• replacing the second and third features with blocks in the first region on the second and third layers respectively, wherein each of the blocks cuts only one of the first features, wherein the blocks in the second and third layers are arranged alternately over the first features;
• and
• manufacturing the IC using at least one mask fabricated with one of the first, second, and third layers.

A method for manufacturing an integrated circuit (IC), comprising:

• receiving a layout of the IC having a first region interposed between two other regions, the first region and the two other regions oriented lengthwise along a first direction,
• wherein the layout includes a first layer having first features oriented lengthwise along a second direction perpendicular to the first direction, the first features traversing the first region and the two other regions,
• wherein the layout further includes a second layer having second features in the first region, the second features oriented lengthwise along the first direction,
• wherein the layout further includes a third layer having third features in the first region, the third features oriented lengthwise along the first direction,
• wherein the second and third features collectively form cut patterns for the first features;
• modifying the second and third features by a computerized mask house tool for improving mask and wafer manufacturability of the layout, resulting in modified second features and modified third features, wherein the modified second and third features collectively form modified cut patterns for the first features;
• and
• manufacturing the IC using at least one mask fabricated with one of the first, second, and third layers.