Automatic gate-level FS analysis and FMEDA

A non-transitory computer readable storage medium comprising instructions that, when executed by one or more processors of a device, cause the device to perform operations comprising:

• accessing register transfer level (RTL) design data for an initial circuit design stored in memory, the initial circuit design comprising a plurality of circuit elements;
• generating safety hierarchy definitions for the initial circuit design;
• generating safety hierarchy associations for the plurality of circuit elements of the initial circuit design and the safety hierarchy definitions;
• generating a Unified Safety Format (USF) file associated with the RTL design data using the safety hierarchy definitions, the safety hierarchy associations, and a set of functional safety (FS) design criteria for the initial circuit design;
• synthesizing a gate-level netlist using the RTL design data and the USF file;
• and
• generating an updated USF file by mapping the safety hierarchy associations for the plurality of circuit elements of the initial circuit design from the RTL design data to the gate-level netlist.

An electronic design automation (EDA) device for generating a circuit design meeting functional safety (FS) design criteria, the EDA device comprising:

• a memory configured to store:
• register transfer level (RTL) design data for the circuit design stored in the memory, the circuit design comprising a plurality of circuit elements;
• and
• a set of functional safety (FS) data associated with an initial circuit design associated with the FS design criteria, the set of FS data describing one or more failure modes associated with the plurality of circuit elements and an associated FS design criterion for each failure mode of the one or more failure modes;
• and
• one or more processors coupled to the memory and configured perform synthesis operations to:
• generate a gate-level netlist using the RTL design data;
• and
• map one or more of associations between the plurality of circuit elements from the RTL design data and the one or more failure modes to the gate-level netlist.