Selective execution for partitioned parallel simulations
AssigneeSynopsys, Inc.
InventorsRamesh Narayanaswamy, Paraminder S. Sahai, Chiahon Chien
Life of this patent
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Abstract
Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design.
Claims28
A computer-implemented method for simulation of an integrated circuit design comprising:
- obtaining a high-level design for simulation;
- determining a graph representation for the high-level design;
- partitioning the graph representation into sub-graphs, wherein the partitioning the graph representation into sub-graphs comprises determining sub-graphs based on levels of logic where the levels of logic are successive stages having sets of primitives with no value dependencies;
- selecting a subset of the sub-graphs for simulation based on input-change bits;
- and
- evaluating the subset of the sub-graphs to produce a simulation result for the high-level design;
- and
- modifying clock gating.
A computer system for simulation of an integrated circuit design, the computer system comprising:
- a memory which stores instructions;
- one or more processors coupled to the memory wherein the one or more processors are configured to:
- obtain a high-level design for simulation;
- determine a graph representation for the high-level design;
- partition the graph representation into sub-graphs, wherein the partitioning the graph representation into sub-graphs comprises determining sub-graphs based on levels of logic where the levels of logic are successive stages having sets of primitives with no value dependencies;
- select a subset of the sub-graphs for simulation based on input-change bits;
- evaluate the subset of the sub-graphs to produce a simulation result for the high-level design;
- and
- modify clock gating.
A computer program product embodied in a non-transitory computer readable medium for simulation of an integrated circuit design, the computer program product comprising:
- code for obtaining a high-level design for simulation;
- code for determining a graph representation for the high-level design;
- code for partitioning the graph representation into sub-graphs, wherein the code for partitioning the graph representation into sub-graphs comprises code for determining sub-graphs based on levels of logic where the levels of logic are successive stages having sets of primitives with no value dependencies;
- code for selecting a subset of the sub-graphs for simulation based on input-change bits;
- code for evaluating the subset of the sub-graphs to produce a simulation result for the high-level design;
- and
- code for modify clock gating.
Dependencies are inferred from the claim text.