US 10,853,543 B1Granted

Logical detection of electronic circuit power sequence risks

OwnerJesse Conrad Newcombinventor

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Abstract

An automated method of determining power sequencing risks (e.g. power-up, power-down time sequences) for complex computer circuits with multiple independent power supplies. The method operates by logical consideration of the topological arrangement of MOSFETs and other devices in standard netlists. The invention inspects the various devices and automatically traces DC circuit paths to DC power rails. The invention then evaluates, as a type of logical existence proof, and on a per MOSFET device level, if due to assignment to different DC power levels, various factors, such as forward-biased diodes, floating MOSFET gate, and other risk factors could ever occur. The method generates comprehensive records of such risks and can output an overall analysis of a circuit reporting on both problematic power sequences, as well as circuit design factors that may be sub-optimal from a power sequence perspective.

Claims15

Dependent claims

A method of logically analyzing an electronic circuit for power sequence risks, said method comprising:

loading an electronic circuit netlist comprising a plurality of MOSFET devices, and paths connecting them, into computer memory;
said MOSFET devices further comprising MOSFET body diodes;
and using at least one computer processor to perform the steps of:
tracing said paths, and determining a plurality of independently driven DC power paths, ground paths, and a corresponding plurality of independently driven DC power rails;
said electronic circuit intended to be operative when said plurality of independently driven DC power paths is driven by said plurality of independently driven DC power rails according to at least one of a plurality of overall power sequences;
for each analyzed MOSFET device in said electronic circuit netlist, scanning said electronic circuit netlist, and determining which of said ground paths and said independently driven DC power paths are connected to said analyzed MOSFET devices;
for each analyzed MOSFET device, determining and storing in at least one data record, for at least those analyzed MOSFET devices with power sequence risks, that said analyzed MOSFET device has a power sequence risk, for at least some overall power sequences, due to any of:
a) forward-biased MOSFET body diode circuit topology;
b) floating or mismatched MOSFET gate-input signal topology;
and using said data records to automatically determine risks in any of said electronic circuit netlist and at least some of said plurality of overall power sequences.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/776,118Filed 29 Jan 2020 · continuation in part
Priority: 29 Mar 2019
Granted: 1 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking
G06F 2119/06
Details relating to the type or aim of the analysis or the optimisation: power analysis or power optimisation
G06F
Computing and data processing

Family

Application62/826,333Us provisional application · filed 29 Mar 2019
Application62/848,922Us provisional application · filed 16 May 2019
Application16/440,875Parent of this continuation-in-part · filed 13 Jun 2019
US 10,878,149 B1Related patent
US 10,853,543 B1This patent

From the US filing history. Foreign family members aren’t listed.