Fuse-based logic repair
AssigneeQUALCOMM Incorporated
InventorsSamit Sengupta, Anil Chowdary Kota, Fadoua Chafik
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Abstract
A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.
Claims20
A method for repairing a logic design, the method comprising:
- inserting primary logic gates in a primary logic design path of a logic chip;
- inserting alternative logic gates in an alternate logic design path of the logic chip;
- coupling the alternate logic design path and the primary logic design path to a plurality of fuses;
- and
- selecting a combination of the alternate logic design path and the primary logic design path, instead of the primary logic design path alone, with the plurality of fuses when the logic design is defective.
An apparatus for repairing a logic design, comprising:
- a memory comprising a programmable fuse bitcell array;
- at least one processor coupled to the memory and configured to read the memory;
- and
- a logic chip comprising:
- a primary logic design path, the primary logic design path comprising primary logic gates, and
- an alternate logic design path, the alternate logic design path comprising alternative logic gates, the alternate logic design path and the primary logic design path coupled to a multiplexer, the memory coupled to the multiplexer and configured to route a programmable signal to the multiplexer to select a combination of the alternate logic design path and the primary logic design path, instead of the primary logic design path alone, based at least in part on a value read from the programmable fuse bitcell array.
A non-transitory computer-readable medium having program code recorded thereon, the program code comprising:
- instructions to select a combination of an alternate logic design path comprising alternative logic gates and a primary logic design path comprising primary logic gates, instead of the primary logic design path alone, with a plurality of fuses when a logic design is defective, the alternative logic design path and the primary logic design path coupled to the plurality of fuses.
Dependencies are inferred from the claim text.