US 10,853,523 B2 · System, method and computer-accessible medium for satisfiability attack resistant logic locking

Abstract

Exemplary embodiment of the present disclosure can include, for example, a logic-locking circuit (“SARLock”), which can include a logic cone(s) receiving a distinguishing input pattern(s) (DIP), a comparator(s) receiving the DIP(s) and a key value(s), and a logic gate(s) connected to an output of the logic cone and to an output of the comparator. A mask(s) can be connected to the comparator(s) and the logic gate(s). The logic gate(s) can be a XOR gate(s). The comparator(s) can be configured to flip a signal(s) based on a combination of the DIP(s) and the key value(s). A mask(s) can be connected to the comparator(s) and the logic gate(s), which can be configured to prevent the flipped signal(s) from being asserted for a correct key value(s).

Claims22

Dependent claims

A logic-locking circuit, comprising:

at least one logic cone receiving at least one distinguishing input pattern (DIP);
at least one comparator receiving the at least one DIP and at least one key value;
and
at least one logic gate connected to (i), an output of the at least one logic cone, and (ii) an output of the at least one comparator, and configured to corrupt the output of the at least one logic cone for at most a predetermined constant number of DIPs for every incorrect key value, based on the output of the at least one comparator.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

16/087,911Filed 20 Mar 2017 · us provisional application

Priority

22 Mar 2016

Published

US 2019/0340394 A17 Nov 2019

Granted

1 Dec 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G01R 31/31719
Testing of digital circuits: security aspects, e.g. preventing unauthorised access during test
G06F 21/75
To assure secure computing or processing of information: by inhibiting the analysis of circuitry or operation
G06F 21/72
To assure secure computing or processing of information: in cryptographic circuits
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

System, method and computer-accessible medium for satisfiability attack resistant logic locking

Life of this patent

System, method and computer-accessible medium for satisfiability attack resistant logic locking

Life of this patent

Abstract

Claims22