Intrusion detection for integrated circuits

An apparatus comprising:

• a wired communications bus configured and arranged to carry data;
• and
• a plurality of integrated circuits, each configured and arranged to interface with the wired communications bus, the plurality of integrated circuits including:
• a first integrated circuit configured and arranged to operate in a scan mode during which the first integrated circuit performs a scan test to detect one or more faults in circuitry of the plurality of integrated circuits;
• and
• a second integrated circuit configured and arranged to operate in a mission mode during which the second integrated circuit supervises data traffic by monitoring communications including data patterns and accesses on the wired communications bus, detecting a suspect illegitimate data communication, and in response, performing a security action to mitigate a suspect illegitimate action in the plurality of integrated circuits, wherein the plurality of integrated circuits includes digital-to-analog conversion circuitry and scan chain circuitry, and wherein the second integrated circuit is further configured and arranged to operate in the mission mode by detecting one or more special data patterns transferred into digital-to-analog conversion circuitry for legitimately testing aspects of the scan chain circuitry.

An apparatus comprising:

• a wired communications bus configured and arranged to carry data;
• and
• a plurality of integrated circuits, each configured and arranged to interface with the wired communications bus, the plurality of integrated circuits including:
• a first integrated circuit configured and arranged to operate in a scan mode during which the first integrated circuit performs a scan test to detect one or more faults in circuitry of the plurality of integrated circuits;
• and
• a second integrated circuit configured and arranged to operate in a mission mode during which the second integrated circuit supervises data traffic by monitoring communications including data patterns and accesses on the wired communications bus, detecting a suspect illegitimate data communication, and in response, performing a security action to mitigate a suspect illegitimate action in the plurality of integrated circuits, wherein the plurality of integrated circuits includes scan chain circuitry configured and arranged for scan testing, and wherein the second integrated circuit is further configured and arranged to operate in the mission mode by detecting an illegitimately access to the plurality of integrated circuits by multiple write-type accesses to a common location of circuitry of data patterns which correspond to counting of bits of a certain portion of the scan chain circuitry, followed by a read-type access.