Digital filter device, digital filtering method, and program recording medium

A digital filter device comprising:

• a first transform circuit configured to execute a first transform process on data in a predetermined frequency range;
• a filtering circuit configured to execute a filtering process by setting an operation bit width of data of a preset first frequency component among the data, on which the first transform process was executed by the first transform circuit, to a different bit width from bit widths of other frequency components;
• and
• a second transform circuit configured to execute a second transform process on the data on which the filtering process was executed by the filtering circuit,
• wherein the first transform circuit is configured to input therein first data in one of first and second orders, and to output, in the second order, second data which are generated by executing the first transform process on the input first data,
• the filtering circuit is configured to input therein the second data in the second order, and to output, in the second order, third data which are generated by executing the filtering process on the input second data,
• the second transform circuit is configured to input therein the third data in the second order, and to output, in one of the first and second orders, fourth data which are generated by executing the second transform process on the input third data, and
• the filtering circuit comprises:
• a first bit width reduction circuit configured to input therein the second data, and to reduce a bit width of data among the input second data;
• a second bit width reduction circuit configured to input therein filter coefficient data for executing the filtering process, and to reduce a bit width of a filter coefficient corresponding to the data whose bit width was reduced by the first bit width reduction circuit;
• an operation circuit configured to execute an operation by using the second data comprising the data whose bit width was reduced by the first bit width reduction circuit, and the filter coefficient data comprising the filter coefficient whose bit width was reduced by the second bit width reduction circuit;
• and
• a bit width extension circuit configured to extend a bit width of data on which the filtering process was executed by the filtering circuit, among the data whose bit width was reduced by the first bit width reduction circuit.