System on chip including clock management unit and method of operating the system on chip

A system on chip (SoC) comprising:

• a first intellectual property (IP) of the SoC configured to generate a first clock request;
• a second IP of the SoC configured to generate a second clock request;
• a first slave clock controller of the SoC;
• a second slave clock controller of the SoC;
• a first master clock controller configured of the SoC to provide a first command to both the first slave clock controller via a first channel and the second slave clock controller via a second channel, in response to the first clock request;
• and
• a second master clock controller of the SoC configured to provide a second command to both the first slave clock controller via a third channel and the second slave clock controller via a fourth channel, in response to the second clock request,
• wherein the first slave clock controller is configured to perform a first clock operation in response to the first command and to provide a first clock acknowledgement to the first master clock controller,
• the second slave clock controller is configured to perform the first clock operation in response to the first command and to provide a second clock acknowledgement to the first master clock controller,
• in response to the first clock acknowledgement and the second clock acknowledgement, the first master clock controller is configured to perform the first clock operation and to provide a first clock signal to the first IP,
• the first slave clock controller is configured to perform a second clock operation in response to the second command and to provide a third clock acknowledgement to the second master clock controller,
• the second slave clock controller is configured to perform the second clock operation in response to the second command and to provide a fourth clock acknowledgement to the second master clock controller, and
• in response to the third clock acknowledgement and the fourth clock acknowledgement, the second master clock controller is configured to perform the second clock operation and to provide a second clock signal to the second IP.

A system comprising:

• a memory;
• a memory controller configured to control an operation of the memory;
• a first IP of an SoC;
• a second IP of the SoC;
• a first slave clock controller of the SoC;
• a second slave clock controller of the SoC;
• and
• a master clock controller of the SoC configured to provide a command to both the first slave clock controller and the second slave clock controller in response to a clock request,
• wherein the first slave clock controller is configured to output a first clock signal in response to the command and to provide a first clock acknowledgement to the master clock controller,
• the second slave clock controller is configured to output a second clock signal in response to the command and to provide a second clock acknowledgement to the master clock controller, and
• in response to the first clock acknowledgement and the second clock acknowledgement, the master clock controller is configured to output a third clock signal to the first IP and/or the second IP.