System, apparatus and method for hardware-based bi-directional communication via reliable high performance half-duplex link
AssigneeIntel Corporation
InventorsAmit Kumar Srivastava, Asad Azam, Rajesh Bhaskar, Mikal Hunsaker, Enrico D. Carrieri
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Abstract
In one embodiment, a host controller includes: a first credit tracker comprising at least one credit counter to maintain credit information for a first device; and a first credit handler to send a command code having a first predetermined value to indicate a credit request to request credit information from the first device, where the first credit tracker is to update the at least one credit counter based on receipt of an in-band interrupt from the first device having the credit information. Other embodiments are described and claimed.
Claims20
An apparatus comprising:
- a host controller to couple to an interconnect to which a plurality of devices may be coupled, the host controller including:
- a first driver to drive first information onto the interconnect;
- a first receiver to receive second information from at least one of the plurality of devices via the interconnect;
- a first set of queues to store information to be communicated to a first device of the plurality of devices;
- a second set of queues to store information to be received from the first device;
- a first credit tracker comprising at least one credit counter to maintain credit information to indicate available buffer space in the first device;
- and
- a first credit handler to send a command code having a first predetermined value to indicate a credit request to request the credit information from the first device, wherein the first credit tracker is to update the at least one credit counter based on receipt of an in-band interrupt from the first device having the credit information.
At least one computer readable storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- receiving, in response to a first credit request from a master device coupled to a plurality of devices via an interconnect, a credit update to identify available buffer space in a first device of the plurality of devices;
- updating at least one credit counter of a link layer of the master device in response to the credit update;
- and
- sending a first packet from the master device to the first device when the available buffer space in the first device is sufficient to accept the first packet.
A system comprising:
- a processor having:
- at least one processing circuit to execute instructions;
- and
- a host controller coupled to the at least one processing circuit to control communication on an interconnect to which a plurality of devices are coupled, the host controller including:
- a credit handler to send a command code having a first predetermined value to request credit information from a first device of the plurality of devices, receive the credit information in a first in-band interrupt from the first device, determine based at least in part on the credit information that the first device has available buffer space to receive a first packet, and, in response to the determination, send the first packet to the first device;
- the interconnect to couple the processor to at least the first device, the interconnect comprising a half-duplex link;
- and
- the first device coupled to the processor via the interconnect, wherein the first device is to send a second in-band interrupt to the processor to initiate an auto-read of data from the first device.
Dependencies are inferred from the claim text.