US 10,853,288 B2Granted

Bus system

AssigneeWAGO Verwaltungsgesellschaft mit beschraenkter Haftung

InventorsRalf Knorr, Christian Voss, Horst Leber

Life of this patent

Estimating the term…

Loading patent…

Abstract

A bus system having a plurality of bus components connected in a bus for the transmission of process data by all bus components, with a master as one of the bus components, with at least one slave as one of the bus components. The master has a master system clock for a master system time. The slave has a slave system clock for a slave system time to be synchronized with the master system time. The master is set up to send a synchronization command at a synchronization time via the bus for the parallel reception by the bus components embodied as slaves. The slave system clock of the slave is set up to calculate and output the slave system time based on the synchronization time received by the data transmission and the synchronization signal time and the current time value of the monotone clock.

Claims13

Dependent claims

A bus system comprising:

a plurality of bus components connected in an order in a bus for a ring-shaped transmission, the bus being configured to transmit process data serially through all bus components in the order;
a master embodied as one of the bus components;
and
at least one slave embodied as one of the bus components,
wherein the master has a master system clock for a master system time,
wherein the slave has a slave system clock for a slave system time to be synchronized with the master system time,
wherein the slave has a shift register that is connected in series with the bus components for transmission of the process data via the bus,
wherein the slave comprises a command circuit and a switching device, the command circuit being adapted to receive at least one synchronization command, and the switching device being connected to receive the synchronization command such that the bus components embodied as slaves are connected in parallel for the reception of the synchronization command,
wherein the master is configured to send the synchronization command via the bus at a synchronization time for parallel reception by the bus components embodied as slaves,
wherein the master is configured to determine the synchronization time,
wherein the command circuit of the slave is configured to output an interrupt signal to the slave system clock upon receipt of the synchronization command,
wherein the slave system clock of the slave has a monotone clock and is adapted to record a time value of the monotone clock at a time of output of the interruption signal as the synchronization signal time,
wherein the master is adapted to send the captured synchronization time via a data transmission to the bus,
wherein the slave is adapted to receive the data transmission via the shift register, the shift register being connected in series with the bus components for the transmission of the data transmission to the bus, and
wherein the slave system clock of the slave is configured to calculate and output the slave system time based on the synchronization time received by the data transmission and the synchronization signal time and the current time value of the monotone clock.

12 more elements

A method for synchronizing a slave system time to a master system time in a bus system having a plurality of bus components, wherein the bus components are connected in an order in a bus for ring-shaped transmission, wherein a master embodied as one of the bus components has a master system clock for the master system time, and wherein at least one slave embodied as one of the bus components has a slave system clock for the slave system time, the method comprising:

transmitting the process data serially through all bus components in the order in the bus, wherein a shift register of the slave is connected in series with the bus components for the transmission of process data via the bus;
receiving at least one synchronization command by a command circuit of the slave;
switching a switching device of the slave for receiving the synchronization command such that bus components embodied as slaves are connected in parallel for receiving the synchronization command;
transmitting the synchronization command for a parallel reception by the bus components embodied as slaves via the bus at a synchronization time point by the master;
outputting an interrupt signal to the slave system clock upon receipt of the synchronization command via the command circuit of the slave;
recording a time value of a monotone clock of the slave system clock at a time the interruption signal is output as the synchronization signal time via the slave system clock of the slave;
determining the synchronization time by the master;
transmitting the determined synchronization time via data transmission to the bus by the master;
receiving the data transmission via the shift register by the slave, wherein the shift register is connected in series with the bus components for sending the data transmission via the bus;
calculating the slave system time by the slave system clock based on the synchronization timing received via the data transmission and the synchronization time and the current time value of the monotone clock;
and
outputting the slave system time by the slave system clock.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/559,107Filed 3 Sep 2019
Priority: DE 10 2018 121 3893 Sep 2018
Published: US 2020/0073838 A15 Mar 2020
Granted: 1 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 13/362
For access to common bus or bus system: with centralised access control
G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…
G06F 1/14
Generating or distributing clock signals or signals derived directly therefrom: time supervision arrangements, e.g. real time clock
G06F
Computing and data processing