Supporting PCI-e message-signaled interrupts in computer system with shared peripheral interrupts

A non-transitory computer readable medium comprising instructions for handling interrupts in a computer system that uses an internal bus for communication between peripheral devices, using shared peripheral interrupt (SPI) vectors, wherein the instructions, when executed by a processor, cause the processor to perform the steps of:

• determining whether a message signaled interrupt (MSI) needs to be allocated for a PCI-e device for an interrupt to be sent to a host;
• when it is determined that MSI needs to be allocated for the PCI-e device, determining whcthcr that neither a Locality Specific Interrupt (LPI) register nor an Interrupt Translation Service (ITS) is available to configure the PCI-e device for LPI or ITS-based MSI generation;
• and
• when it is determined that neither the LPI register nor the Interrupt Translation Service (ITS) is available to process the interrupt, determining an available SPI vector and configuring the PCI-e device for SPI-based MSI generation by assigning the available SPI vector to the PCI-e device.

A computer system, comprising:

• an internal bus;
• a plurality of peripheral devices communicable with each other via the internal bus;
• and
• a processor configured to carry out the steps of:
• determining whether a message signaled interrupt (MSI) needs to be allocated for a PCI-e device for an interrupt to be sent to a host;
• when it is determined that MSI needs to be allocated for the PCI-e device, determining that neither a Locality Specific Interrupt (LPI) register nor an Interrupt Translation Service (ITS) is available to process the interrupt;
• and
• when it is determined that neither the LPI register nor the Interrupt Translation Service (ITS) is available to process the interrupt, configuring the PCI-e device for SPI-based MSI generation to route the interrupt by assigning an available SPI vector to the PCI-e device.