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US 10,853,278 B2Granted
Memory system
AssigneeSK hynix Inc.
InventorsSun Woong Kim, Eui Cheol Lim
Life of this patent
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Abstract
A memory system is disclosed, which relates to technology for an accelerator of a high-capacity memory device. The memory system includes a plurality of memories configured to store data therein, and a pooled memory controller (PMC) configured to perform map computation by reading the data stored in the plurality of memories and storing resultant data produced by the map computation in the plurality of memories.
Claims17
A memory system, comprising:
- a plurality of memories configured to store data therein;
- and
- a pooled memory controller configured to perform a map computation and storing resultant data of the map computation in the plurality of memories, wherein the pooled memory controller includes:
- an interface configured to perform packet relay between at least one processor and at least one memory through a fabric network;
- and
- an accelerator configured to perform the map computation by reading an input data received from the plurality of memories through the interface to produce the resultant data, wherein the accelerator is coupled to the interface through a plurality of channels;
- wherein the interface transmits the read input data to the accelerator, and receives the resultant data computed by the accelerator, and transmits the received resultant data to the plurality of memories, and
- wherein a number of links of the plurality of channels is higher than a number of links between the interface and any one of the processors.
5 more elements
A memory system comprising:
- a fabric network coupled to at least one processor;
- and
- a pooled memory having a plurality of memories and a pooled memory controller, the pooled memory being configured to perform packet relay to the processor through the fabric network, and transmit data stored in at least one memory in response to a request from the processor,
- wherein the pooled memory controller is configured to perform off-loading of a map computation by reading input data stored in the at least one memory and storing in the at least one memory resultant data of the map computation in the plurality of memories,
- wherein the pooled memory controller includes:
- an interface configured to perform packet relay between the at least one processor and the pooled memory controller through the fabric network, wherein the interface is coupled to the accelerator through a plurality of channels;
- and
- an accelerator configured to perform the map computation and the off-loading of the map computation by reading an input data received from the plurality of memories through the interface to produce the resultant data, wherein the accelerator is coupled to the interface through a plurality of channels,
- wherein the interface transmits the read input data to the accelerator, and receives the resultant data computed by the accelerator, and stores the received resultant data in the plurality of memories, and
- wherein a number of links of the plurality of channels is higher than a number of links between the interface and any one of the processors.
7 more elements
Dependencies are inferred from the claim text.