Memory access protection apparatus and methods for memory mapped access between independently operable processors
AssigneeApple Inc.
InventorsSaurabh Garg, Karan Sanghi, Vladislav Petkov, Haining Zhang
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Abstract
Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.
Claims20
A method for handling detected violations of host memory by a peripheral processor apparatus, the method comprising:
- detecting an access violation associated with a defined extent of address space within the host memory;
- transmitting a nullified packet comprising an inverted data link layer cyclic redundancy check (LCRC) value to a host processor apparatus in response to the detected access violation;
- transmitting a violation message to a violation register;
- while the violation message has not been cleared, preventing transmission of one or more data packets by the peripheral processor apparatus;
- and
- responsive to the violation message being cleared, enabling transmission of the one or more data packets to the host processor apparatus by the peripheral processor apparatus.
A computing device comprising a memory mapped system, the computing device comprising:
- a host processing device;
- a peripheral processing device;
- and
- a host memory accessible by both the host processing device and the peripheral processing device;
- wherein the peripheral processing device is configured to:
- detect an access violation outside of a defined extent of address space within the host memory;
- in response to the detected access violation, transmit a nullified packet to the host processing device;
- store a violation message within a violation register;
- while the violation message has not been cleared, prevent transmission of one or more data packets by the peripheral processing device to the host processing device;
- and
- responsive to the violation message being cleared, enable transmission of the one or more data packets to the host processing device by the peripheral processing device;
- and
- wherein the nullified packet comprises a value associated with an inverted data link layer cyclic redundancy check (LCRC).
A peripheral processor apparatus for use in a system that comprises the peripheral processor apparatus and a host processor apparatus, the peripheral processor apparatus configured to:
- detect an access violation outside a defined extent of address space within host memory;
- in response to the detected access violation, transmit a nullified packet to the host processor apparatus;
- transmit a violation message to a violation register;
- and
- responsive to the violation message being cleared, cause transmission of one or more data packets to the host processor apparatus;
- wherein the transmission of the nullified packet comprises a transmission of a transaction layer packet (TLP), the TLP comprising an inverted data link cyclic redundancy check (LCRC) value.
Dependencies are inferred from the claim text.