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US 10,853,265 B2Granted
Address mapping in memory systems
AssigneeRambus Inc.
InventorsHongzhong Zheng, James Tringali
Life of this patent
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Abstract
A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.
Claims20
A memory controller, comprising:
- an address mapping circuit to receive an input memory address comprising a first bit group indicating an input row address and a second bit group indicating an input column address, the address mapping circuit applying a logic function to at least a portion of the input row address and at least a portion of the input column address, in a first operation, to generate a mapped column address, the address mapping circuit, in a second operation, to reassign the input column address as a mapped row address;
- and
- an output interface to communicate the mapped column address and the mapped row address to an integrated circuit (IC) memory device.
A method of operating a memory controller, comprising:
- receiving an input memory address with an address mapping circuit, the input memory address comprising a first bit group indicating a row address and a second bit group indicating a column address;
- in a first operation, applying a logic function to at least a portion of the input row address and at least a portion of the input column address, with the address mapping circuit, to generate a mapped column address;
- in a second operation, reassigning the input column address as a mapped row address, with the address mapping circuit;
- and
- transferring the mapped column address and the mapped row address to an integrated circuit (IC) memory device via an output interface.
2 more elements
An integrated circuit (IC) chip, comprising:
- memory control circuitry including
- an address mapping circuit to receive an input memory address comprising a first bit group indicating a row address and a second bit group indicating a column address, the address mapping circuit applying a logic function to at least a portion of the input row address and at least a portion of the input column address in a first operation to generate a mapped column address, the address mapping circuit, in a second operation, to reassign the input column address as a mapped row address;
- and
- an output interface to communicate the mapped column address and the mapped row address to an integrated circuit (IC) memory device.
1 more element
Dependencies are inferred from the claim text.