Memory address translation using stored key entries

#This application is the U.S. national phase of International Application No. PCT/GB2017/053588 filed Nov. 29, 2017 which designated the U.S. and claims priorities to GR 20160100608 filed Nov. 29, 2016, and GR 20170100521 filed Nov. 22, 2017, the entire contents of each of which are hereby incorporated by reference.

#This disclosure relates to memory address translation.

#Memory address translation apparatus, such as management units (MMUs), attend to the translation of virtual memory addresses into physical memory addresses.

#The present technique will be described further, by way of example only, with reference to embodiments thereof as illustrated in the accompanying drawings, in which:

#FIG. 1 illustrates an apparatus in accordance with some embodiments;

#FIG. 2 illustrates an apparatus in accordance with some embodiments;

#This description relates to a number of potentially orthogonal techniques, which may be used together in any combination. FIG. 1 illustrates an example apparatus 100 in which all the techniques to be discussed below are used simultaneously. The apparatus includes a plurality of processors 105a, 105b . . . , each having a dedicated Translation Lookaside Buffer 110a, 110b, . . . for the translation of an input address to an output address in an output space. Each processor is able to send maintenance operations, lookup operations, and fill operations to an interconnect 125 via one or more input ports 135. Each of these operations relates to address storage 155 (which can act as a translation data buffer) associated with the interconnect 125. The lookup operations comprise an input or initial address for which an output address in an output space is to be provided. The fill operations are used to provide such translations. Meanwhile, a maintenance queue 145 stores the maintenance operations, which are performed asynchronously by the maintenance circuitry 150 on the address storage 155 so that the processor 105a need not wait for the maintenance operations to be performed. The address storage 155 may take the form of circuitry to access a further TLB, for which the translation data may actually be stored in the memory 115 and which can also access the memory 115 for so-called page table walks to populate the address storage. The interconnect 125 provides a connection to a main memory 115 via one or more output ports 140. The main memory is controlled via a controller 120. Data read from or to be written to the main memory 115 can be stored in a cache 160, which is associated with the interconnect 125. By providing a cache, the processors 105a, 105b, . . . can access data from the memory 115 more quickly than if a request has to be sent out of the interconnect 125 and handled by the memory controller 120. Storage from the cache 160 can be ‘stolen’ (temporarily or otherwise reallocated) for use by the address storage 155 so that the amount of storage available for storing address translations can be increased beyond the capacity of the address storage 155 itself. The management of the stolen storage, as well as the operation of the maintenance queue 145, address storage 155, and cache 160 is handled by the control circuitry 130. The control circuitry can control the timing of page table walks and TLB accesses so that for a particular translation request from the TLB 110a, the page table walk can be initiated before completion of a TLB lookup. The controller 120 and the control circuitry 130 can cooperate to oversee the storage in and retrieval from the memory 115 of translation data in the form of key-value pairs such that in some examples multiple such pairs can be stored in a single row of memory cells (accessible by a row buffer (not shown) of the memory 115) of the memory 115. Note that the main memory 115 and the cache 160 itself could be implemented by using DRAM.

#Asynchronous Maintenance

#FIG. 2 illustrates an example of an apparatus 200 in accordance with some embodiments. This apparatus comprises a set of inputs ports 210, which provide lookup operations and maintenance operations (collectively referred to as ‘requests’) to a control circuitry 240. Lookup operations having the input address (lookup requests) are passed to the lookup circuitry 230, which could for instance take the form of a Translation Lookaside Buffer (TLB). In some embodiments, the TLB could be provided via DRAM. Maintenance operations (maintenance requests) are passed to a maintenance queue 220. Such apparatus 200 may be used for providing asynchronous maintenance in a storage system and is provided as an example of an apparatus 200 comprising an input port 210 to receive, from a requester, any one of: a lookup operation comprising an input address, and a maintenance operation; maintenance queue circuitry 220 to store a maintenance queue of at least one maintenance operation; and address storage (for example, implemented by the lookup circuitry 230) to store a translation between the input address and an output address in an output address space, wherein in response to receiving the input address, the output address is provided in dependence on the maintenance queue; and in response to storing the maintenance operation, the maintenance queue circuitry causes an acknowledgement to be sent to the requester.