Methods and apparatuses for addressing memory caches

A method of operating a cache memory, comprising:

• storing first information associated with a first physical address in a first cache line in a cache line array on a die, the first physical address being one of a plurality of physical addresses each comprising at least first and second non-overlapping, distinct predefined portions, the cache line array including cache lines indexed by the second portions of the plurality of physical addresses, the first cache line corresponding to the second portion of the first physical address;
• updating a first entry in one or more tables to indicate that the first cache line has been allocated to store the first information, each table of the one or more tables including a plurality of entries indexed by the first portions of the plurality of physical addresses, the first entry corresponding to the first portion of the first physical address;
• and
• determining, using circuitry coupled to the one or more tables, whether the one or more tables include a second entry corresponding to the first portion of a second physical address and storing an indication that a second cache line corresponding to the second portion of the second physical address has been allocated to store second information associated with the second physical address.

A memory system, comprising:

• a semiconductor package;
• a first die coupled to the semiconductor package;
• cache lines on the first die to store information associated with physical addresses, each physical address comprising at least first and second non-overlapping, distinct predefined portions, the cache lines being indexed by the second portions of respective physical addresses;
• one or more tables on a second die in the semiconductor package, each table comprising table entries indexed by the first portions of the respective physical addresses, wherein a respective table entry in each of the one or more tables is to store indications of whether any one or more of a plurality of cache lines have been allocated to store information;
• logic circuitry coupled to the one or more tables, to output a cache hit signal upon determining that the one or more tables include a table entry corresponding to the first portion of a specified physical address and storing an indication that a cache line corresponding to the second portion of the specified physical address has been allocated to store information associated with the specified physical address;
• and
• output circuitry coupled to the cache lines, to forward the information associated with the specified physical address from the cache line corresponding to the second portion of the specified physical address in accordance with the cache hit signal.