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US 10,853,254 B2Granted
Memory system having a memory controller and a memory device having a page buffer
AssigneeSK hynix Inc.
InventorJeen Park
Life of this patent
Estimating the term…
Abstract
There are provided a memory controller and a memory system having the same. A memory controller includes: a command queue for queuing commands and outputting command information including Information of a previous command and a subsequent command; a command detector for outputting a detection signal according to the command information; and a command generator for generating the command and outputting a management command for managing a last command immediately following the previous command in response to the detection signal.
Claims14
A memory system comprising:
- a memory device including a page buffer for temporarily storing data read from a memory cell, the page buffer including first to third latches temporarily storing or transferring the data;
- and
- a memory controller coupled to the memory device through a channel,
- wherein the memory controller controls the memory device such that the first to third latches are selectively reset according to a previous operation performed in the memory device and a subsequent operation to be performed in the memory device,
- wherein the first latch coupled to the memory cell through a bit line stores data sensed from the memory cell, and the second latch transfers the data between the first and third latches and temporarily stores the data when the data of the memory cell is sensed in the first latch or the data in the third latch is outputted to the memory controller,
- wherein the first to third latches are reset when the subsequent operation is different from the previous operation, and
- wherein the first latch is kept or reset and the second and third latches are kept when the subsequent operation is the same as the previous operation.
4 more elements
A memory system comprising:
- a memory device including a memory cell storing data and first to third latches, wherein the first latch is coupled to the memory cell through a bit line, the second latch is coupled between the first and third latches, and the third latch outputs the data;
- and
- a memory controller configured to control the memory device to simultaneously perform a data sensing operation and an output operation in response to a cache read command,
- wherein the memory controller includes:
- a command queue configured to queue the cache read command and output command information including information of a subsequent command of the cache read command;
- a command detector configured to determine whether the subsequent command is sequential from the previous command according to the command information, and selectively output a detection signal among detection signals in response to a result of the determination;
- and
- a command generator configured to generate a management command for selectively resetting the first to third latches in a memory device in response to the detection signal,
- wherein the first latch stores the data sensed from the memory cell, and the second latch transfers the data between the first and third latches and temporarily stores the data when the data of the memory cell is sensed in the first latch or the data in the third latch is outputted to the memory controller,
- wherein the first to third latches are reset when a subsequent operation is different from a previous operation, and
- wherein the first latch is kept or reset and the second and third latches are kept when the subsequent operation is the same as the previous operation.
8 more elements
Dependencies are inferred from the claim text.