Device for maintaining data consistency between hardware accelerator and host system and method thereof

A method of maintaining data consistency between a hardware accelerator and a host system, wherein the method is at least temporarily implemented by a computer, and comprises:

• transferring arguments from a user program to a hardware accelerator API (Application Programming Interface);
• calling at least one of write-back and invalidate functions in the hardware accelerator based on properties of the arguments;
• determining whether an address which the hardware accelerator should access is present in a cache;
• and
• when the address is present in the cache, performing at least one of write-back and invalidation processes on the corresponding address in the cache according to at least one of the called write-back and invalidate functions;
• and controlling the hardware accelerator to be activated when at least one of the write-back and invalidation processes is completed,
• wherein the calling comprises classifying properties of the arguments into reference process, overwrite process, temporary process and complex process and calling at least one of the write-back and invalidate functions based on the properties of the arguments,
• wherein an address range that a processor accesses is divided into non-cacheable addresses and cacheable addresses, and the method comprises accessing only the cacheable addresses to execute computer-readable instructions for performing the method,
• wherein the performing comprises performing the write-back process on data in the cache to a main memory and controlling the data in the cache to be maintained in the reference process,
• wherein the performing comprises performing the invalidation process on the data in the cache, controlling data in the main memory to be maintained, removing the data in the cache and performing overwriting on the data in the main memory in the overwrite process,
• wherein the performing comprises performing the invalidation process on the data in the cache and the performing the write-back process on the data in the cache to the main memory in the complex process,
• wherein the write-back process and the invalidation process of the cache are performed in a cache line of the cache,
• wherein the write-back process is performed on the cache line to update data to the main memory and the invalidation process is performed on the cache line based on the cache line containing data associated with the hardware accelerator and data not associated with the hardware accelerator, and
• wherein the invalidation process is performed on the cache line based on the cache line containing only data associated with the hardware accelerator.