Real-time input/output bandwidth estimation
AssigneeIntel Corporation
InventorAdrian Loteanu
Life of this patent
Estimating the term…
Abstract
A bandwidth estimation method is disclosed for measuring memory bandwidth consumption or the bandwidth consumption of any I/O bus in real time on a computer system without the use of hardware counters. The bandwidth estimation method, designed to run in isolation on a core in a multi-core computer system, generates temporally sequential and spatially random accesses to a bus such as the memory bus and reports the average latency per request. Using a pre-calculated latency-bandwidth relationship, the bandwidth on the bus is calculated and reported at runtime for every latency sample. The bandwidth estimation method allows profiling processors and computer systems in real time to determine the amount of memory or I/O traffic they are using while running a workload.
Claims20
An apparatus comprising:
- a processor comprising a plurality of cores, the plurality of cores comprising a first core and remaining cores;
- memory coupled to the processor by a bus, the memory comprising instructions executable by the processor which, when executed, cause the processor to:
- inject, via the plurality of cores, a predetermined amount of traffic onto the bus;
- determine a dependency between latency and bandwidth of the bus based on the predetermined amount of traffic;
- generate a function that, given a latency, will return an associated bandwidth based on the dependency;
- execute, via the remaining cores, one or more workloads;
- generate, by the first core, a plurality of memory accesses via the bus;
- and
- calculate the bandwidth of the bus consumed by the one or more workloads based in part on the plurality of memory accesses and the function.
A method comprising:
- injecting, via a plurality of cores of a processor, a predetermined amount of traffic onto a memory bus, the memory bus to couple a memory to the processor, the plurality of cores comprising a first core and remaining cores;
- determining a dependency between latency and bandwidth of the memory bus based on the predetermined amount of traffic;
- generating a function that, given a latency, will return an associated bandwidth based on the dependency;
- executing, via the remaining cores, one or more workloads;
- generating, by the first core, a plurality of accesses to the memory via the memory bus;
- and
- calculating the bandwidth of the memory bus consumed by the one or more workloads based in part on the plurality of accesses to the memory and the function.
At least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processor, cause the processor to:
- inject, via a plurality of cores of the processor, a predetermined amount of traffic onto a bus coupling the processor to a device, the plurality of cores further comprising a first core and remaining cores;
- determine a dependency between latency and bandwidth of the bus based on the predetermined amount of traffic;
- generate a function that, given a latency, will return an associated bandwidth based on the dependency;
- execute, via the remaining cores, one or more workloads;
- generate, by the first core, a plurality of accesses to the device via the bus;
- and
- calculate the bandwidth of the bus consumed by the one or more workloads based in part on the plurality of accesses to the device and the function.
Dependencies are inferred from the claim text.