Memory controller, semiconductor memory system including the same, and method of driving the semiconductor memory system

A semiconductor memory system comprising:

• a memory device including a memory cell array and a control circuit block, the memory cell array including a plurality of memory cells arranged in a matrix shape with n rows and m columns, m and n being positive integers, the control circuit block being arranged at an edge portion of the memory cell array;
• and
• a memory controller configured to provide the memory device with write data, a read command, a write command, and addresses providing positions at which the write data is written in the memory device,
• wherein the memory controller comprises:
• an ECC circuit configured to correct read data;
• a data determination block configured to generate an address change signal when a number of the write data having a first logic level is within a correctable range of the ECC circuit;
• and
• an address control block configured to remap a write target address with an address of a memory cell adjacent to the control circuit block in a write operation when a datum corresponding to the write target address has the first logic level and when the adjacent memory cell is empty, and to select, in a read operation, one of a read target address and a remapping address based on remapping information of the read target address.

A method of driving a semiconductor memory system, the memory system including a memory device and a memory controller, the memory device including a memory cell array and a control circuit block, the memory cell array including a plurality of memory cells, the control circuit block being arranged at an edge portion of the memory cell array, the memory controller being configured to control operations of the memory device, the method comprising:

• counting a number of write data having a first logic level;
• determining whether the number of the write data having the first logic level is within a correctable range;
• remapping a write target address on an address of one of the memory cells adjacent to the control circuit block when the number of the write data having the first logic level is determined to be within the correctable range and a datum corresponding to the write target address has the first logic level;
• storing the datum of the write target address in the adjacent memory cell corresponding to the remapped address;
• identifying, when a read command is issued, whether remapping information corresponds to a read target address by determining whether the remapping information is stored in a row table corresponding to the read target address or a column table corresponding to the read target address;
• reading a datum in the adjacent memory cell based on the remapping information when the remapping information corresponds to the read target address;
• and
• reading a datum in a target memory cell corresponding to the read target address when the remapping information does not correspond to the read target address,
• wherein the method further comprises inputting the write data into the memory device when the memory controller issues a write command.