Memory apparatus having hierarchical error correction code layer
AssigneeWinbond Electronics Corp.
InventorsChuen-Der Lien, Ming-Huei Shieh, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
Life of this patent
Estimating the term…
Abstract
The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N−1 pre-set error correction number(s), and N is a positive integer larger than 1.
Claims13
A memory apparatus, comprising:
- a memory cell array;
- and
- a hierarchical error correction code (ECC) layer, comprising N layers of ECC coder-decoder,
- wherein, the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when an error bit number of the processed data reaches to N−1 pre-set error correction number(s),
- wherein N is a positive integer larger than 1.
Dependencies are inferred from the claim text.