Memory-based software barriers
AssigneeIntel Corporation
InventorsAltug Koker, Joydeep Ray, Balaji Vembu, James A. Valerio, Abhishek R. Appu
Life of this patent
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Abstract
A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.
Claims17
An apparatus comprising:
- one or more processors including a graphics processor, the one or more processors to process a plurality of threads;
- wherein the one or more processors include a plurality of hardware barriers;
- and
- wherein the one or more processors are to:
- assign one or more barriers to each of one or more thread groups, wherein the one or more barriers include one or more hardware barriers of the plurality of hardware barriers, one or more software barriers, or both,
- track barrier resources for thread scheduling, including tracking of whether each assigned barrier is a hardware barrier or a software barrier, and
- upon assigning a first software barrier to a first thread group of the one or more thread groups, the first software barrier being assigned in response to a determination that a number of available hardware barriers is insufficient for scheduling of the plurality of threads, transmit a barrier message to a data port unit identifying the first software barrier.
A method comprising:
- assigning one or more barriers to each of one or more thread groups for a computing system, wherein the one or more barriers include one or more hardware barriers of a plurality of hardware barriers, one or more software barriers, or both;
- tracking barrier resources for thread scheduling for the computing system, including tracking of whether each assigned barrier is a hardware barrier or a software barrier;
- and
- upon assigning a first software barrier to a first thread group of the one or more thread groups, the first software barrier being assigned in response to a determination that a number of available hardware barriers is insufficient for scheduling of a plurality of threads for the computing system, transmitting a barrier message to a data port unit identifying the first software barrier.
At least one non-transitory machine-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- assigning one or more barriers to each of one or more thread groups for a computing system, wherein the one or more barriers include one or more hardware barriers of a plurality of hardware barriers, one or more software barriers, or both;
- tracking barrier resources for thread scheduling for the computing system, including tracking of whether each assigned barrier is a hardware barrier or a software barrier;
- and
- upon assigning a first software barrier to a first thread group of the one or more thread groups, the first software barrier being assigned in response to a determination that a number of available hardware barriers is insufficient for scheduling of a plurality of threads for the computing system, transmitting a barrier message to a data port unit identifying the first software barrier.
Dependencies are inferred from the claim text.