Memory module
AssigneeRenesas Electronics Corporation
InventorTatsuhiro Tachibana
Life of this patent
Estimating the term…
Abstract
The access control circuit writes to the first storage unit a context information transmitted in one cycle from the CPU through the first bus, a context number identifying the context information, and a link context number identifying the context information transmitted from the CPU prior to the interrupt when the request for evacuating the task context information is received by the interrupt. After writing to the first storage unit, the access control circuit transfers the data including the context information and the link context number stored in the first storage unit to the second storage unit in a plurality of cycles through the internal bus (second bus) in association with the context number stored in the first storage unit.
Claims16
A memory module comprising:
- a first storage unit coupled to a central processing unit (CPU) through a first bus having a first bit width;
- a second storage unit coupled to the first storage unit through a second bus having a bit width smaller than the first bit width;
- and
- an access control circuit that writes, into the first storage unit when a request to save context information of a task is received by an interrupt, 1) context information transferred from the CPU in one cycle through the first bus, 2) a context number identifying the context information, and 3) a link context number being a context number identifying context information transferred from the CPU to the first storage unit at a time of a previous interrupt,
- wherein after writing into the first storage unit, the access control circuit 1) corresponds data comprising the context information and the link context number stored in the first storage unit to the context number, and 2) transfers the data to an address of the second storage unit through the second bus in a plurality of cycles.
A memory module comprising:
- a first storage unit coupled to a central processing unit (CPU) through a first bus having a first bit width, wherein the first storage unit is configured to store context data including 1) context information, 2) a context number identifying the context information, and 3) a link context number being a context number identifying context information transferred from the CPU at a time of a previous interrupt, for each of tasks which have stopped execution by each of a plurality of interrupts;
- a second storage unit coupled to the first storage unit through a second bus having a bit width smaller than the first bit width;
- and
- an access control circuit,
- wherein, when a request to save context information of a task is received by an interrupt and when the first storage unit does not have an area for storing latest context data including 1) context information transferred from the CPU through the first bus in a one cycle, 2) a context number identifying the context information, and 3) a link context number being a context number identifying context information transferred from the CPU to the first storage unit at a time of a previous interrupt, the access control unit deletes at least a part of context data already stored in the first storage unit, and then writes the latest context data to the first storage unit, and
- wherein the access control circuit transfers the latest context data stored in the first storage unit to the second storage unit through the second bus in one or more cycles.
Dependencies are inferred from the claim text.